Port flag-based ops to ISLE (AArch64) (#4942)

Ported the existing implementations of the following opcodes for AArch64
to ISLE:
- `Trueif`
- `Trueff`
- `Trapif`
- `Trapff`
- `Select`
- `Selectif`
- `SelectifSpectreGuard`

Copyright (c) 2022 Arm Limited

cranelift/filetests/filetests/isa/aarch64/condops.clif

@@ -2,6 +2,48 @@ test compile precise-output
 set unwind_info=false
 target aarch64
 
+function %f(i8, i8, i8) -> i8 {
+block0(v0: i8, v1: i8, v2: i8):
+  v3 = iconst.i8 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i8 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxtb w5, w0
+;   subs wzr, w5, #42
+;   csel x0, x1, x2, eq
+;   ret
+
+function %f(i8, i16, i16) -> i16 {
+block0(v0: i8, v1: i16, v2: i16):
+  v3 = iconst.i8 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i16 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxtb w5, w0
+;   subs wzr, w5, #42
+;   csel x0, x1, x2, eq
+;   ret
+
+function %f(i8, i32, i32) -> i32 {
+block0(v0: i8, v1: i32, v2: i32):
+  v3 = iconst.i8 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i32 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxtb w5, w0
+;   subs wzr, w5, #42
+;   csel x0, x1, x2, eq
+;   ret
+
 function %f(i8, i64, i64) -> i64 {
 block0(v0: i8, v1: i64, v2: i64):
   v3 = iconst.i8 42
@@ -11,11 +53,690 @@ block0(v0: i8, v1: i64, v2: i64):
 }
 
 ; block0:
-;   uxtb w6, w0
-;   subs wzr, w6, #42
+;   uxtb w5, w0
+;   subs wzr, w5, #42
 ;   csel x0, x1, x2, eq
 ;   ret
 
+function %f(i8, i128, i128) -> i128 {
+block0(v0: i8, v1: i128, v2: i128):
+  v3 = iconst.i8 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i128 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxtb w8, w0
+;   subs wzr, w8, #42
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   ret
+
+function %f(i16, i8, i8) -> i8 {
+block0(v0: i16, v1: i8, v2: i8):
+  v3 = iconst.i16 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i8 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxth w5, w0
+;   subs wzr, w5, #42
+;   csel x0, x1, x2, eq
+;   ret
+
+function %f(i16, i16, i16) -> i16 {
+block0(v0: i16, v1: i16, v2: i16):
+  v3 = iconst.i16 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i16 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxth w5, w0
+;   subs wzr, w5, #42
+;   csel x0, x1, x2, eq
+;   ret
+
+function %f(i16, i32, i32) -> i32 {
+block0(v0: i16, v1: i32, v2: i32):
+  v3 = iconst.i16 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i32 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxth w5, w0
+;   subs wzr, w5, #42
+;   csel x0, x1, x2, eq
+;   ret
+
+function %f(i16, i64, i64) -> i64 {
+block0(v0: i16, v1: i64, v2: i64):
+  v3 = iconst.i16 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i64 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxth w5, w0
+;   subs wzr, w5, #42
+;   csel x0, x1, x2, eq
+;   ret
+
+function %f(i16, i128, i128) -> i128 {
+block0(v0: i16, v1: i128, v2: i128):
+  v3 = iconst.i16 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i128 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxth w8, w0
+;   subs wzr, w8, #42
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   ret
+
+function %f(i32, i8, i8) -> i8 {
+block0(v0: i32, v1: i8, v2: i8):
+  v3 = iconst.i32 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i8 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs wzr, w0, #42
+;   csel x0, x1, x2, eq
+;   ret
+
+function %f(i32, i16, i16) -> i16 {
+block0(v0: i32, v1: i16, v2: i16):
+  v3 = iconst.i32 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i16 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs wzr, w0, #42
+;   csel x0, x1, x2, eq
+;   ret
+
+function %f(i32, i32, i32) -> i32 {
+block0(v0: i32, v1: i32, v2: i32):
+  v3 = iconst.i32 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i32 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs wzr, w0, #42
+;   csel x0, x1, x2, eq
+;   ret
+
+function %f(i32, i64, i64) -> i64 {
+block0(v0: i32, v1: i64, v2: i64):
+  v3 = iconst.i32 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i64 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs wzr, w0, #42
+;   csel x0, x1, x2, eq
+;   ret
+
+function %f(i32, i128, i128) -> i128 {
+block0(v0: i32, v1: i128, v2: i128):
+  v3 = iconst.i32 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i128 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs wzr, w0, #42
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   ret
+
+function %f(i64, i8, i8) -> i8 {
+block0(v0: i64, v1: i8, v2: i8):
+  v3 = iconst.i64 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i8 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs xzr, x0, #42
+;   csel x0, x1, x2, eq
+;   ret
+
+function %f(i64, i16, i16) -> i16 {
+block0(v0: i64, v1: i16, v2: i16):
+  v3 = iconst.i64 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i16 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs xzr, x0, #42
+;   csel x0, x1, x2, eq
+;   ret
+
+function %f(i64, i32, i32) -> i32 {
+block0(v0: i64, v1: i32, v2: i32):
+  v3 = iconst.i64 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i32 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs xzr, x0, #42
+;   csel x0, x1, x2, eq
+;   ret
+
+function %f(i64, i64, i64) -> i64 {
+block0(v0: i64, v1: i64, v2: i64):
+  v3 = iconst.i64 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i64 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs xzr, x0, #42
+;   csel x0, x1, x2, eq
+;   ret
+
+function %f(i64, i128, i128) -> i128 {
+block0(v0: i64, v1: i128, v2: i128):
+  v3 = iconst.i64 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i128 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs xzr, x0, #42
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   ret
+
+function %f(i128, i8, i8) -> i8 {
+block0(v0: i128, v1: i8, v2: i8):
+  v3 = iconst.i128 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i8 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   movz x6, #42
+;   movz x8, #0
+;   subs xzr, x0, x6
+;   ccmp x1, x8, #nzcv, eq
+;   csel x0, x2, x3, eq
+;   ret
+
+function %f(i128, i16, i16) -> i16 {
+block0(v0: i128, v1: i16, v2: i16):
+  v3 = iconst.i128 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i16 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   movz x6, #42
+;   movz x8, #0
+;   subs xzr, x0, x6
+;   ccmp x1, x8, #nzcv, eq
+;   csel x0, x2, x3, eq
+;   ret
+
+function %f(i128, i32, i32) -> i32 {
+block0(v0: i128, v1: i32, v2: i32):
+  v3 = iconst.i128 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i32 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   movz x6, #42
+;   movz x8, #0
+;   subs xzr, x0, x6
+;   ccmp x1, x8, #nzcv, eq
+;   csel x0, x2, x3, eq
+;   ret
+
+function %f(i128, i64, i64) -> i64 {
+block0(v0: i128, v1: i64, v2: i64):
+  v3 = iconst.i128 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i64 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   movz x6, #42
+;   movz x8, #0
+;   subs xzr, x0, x6
+;   ccmp x1, x8, #nzcv, eq
+;   csel x0, x2, x3, eq
+;   ret
+
+function %f(i128, i128, i128) -> i128 {
+block0(v0: i128, v1: i128, v2: i128):
+  v3 = iconst.i128 42
+  v4 = ifcmp v0, v3
+  v5 = selectif.i128 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   movz x9, #42
+;   movz x11, #0
+;   subs xzr, x0, x9
+;   ccmp x1, x11, #nzcv, eq
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   ret
+
+function %f(i8, i8, i8) -> i8 {
+block0(v0: i8, v1: i8, v2: i8):
+  v3 = iconst.i8 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i8 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxtb w5, w0
+;   subs wzr, w5, #42
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
+
+function %f(i8, i16, i16) -> i16 {
+block0(v0: i8, v1: i16, v2: i16):
+  v3 = iconst.i8 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i16 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxtb w5, w0
+;   subs wzr, w5, #42
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
+
+function %f(i8, i32, i32) -> i32 {
+block0(v0: i8, v1: i32, v2: i32):
+  v3 = iconst.i8 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i32 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxtb w5, w0
+;   subs wzr, w5, #42
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
+
+function %f(i8, i64, i64) -> i64 {
+block0(v0: i8, v1: i64, v2: i64):
+  v3 = iconst.i8 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i64 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxtb w5, w0
+;   subs wzr, w5, #42
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
+
+function %f(i8, i128, i128) -> i128 {
+block0(v0: i8, v1: i128, v2: i128):
+  v3 = iconst.i8 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i128 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxtb w8, w0
+;   subs wzr, w8, #42
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   csdb
+;   ret
+
+function %f(i16, i8, i8) -> i8 {
+block0(v0: i16, v1: i8, v2: i8):
+  v3 = iconst.i16 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i8 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxth w5, w0
+;   subs wzr, w5, #42
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
+
+function %f(i16, i16, i16) -> i16 {
+block0(v0: i16, v1: i16, v2: i16):
+  v3 = iconst.i16 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i16 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxth w5, w0
+;   subs wzr, w5, #42
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
+
+function %f(i16, i32, i32) -> i32 {
+block0(v0: i16, v1: i32, v2: i32):
+  v3 = iconst.i16 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i32 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxth w5, w0
+;   subs wzr, w5, #42
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
+
+function %f(i16, i64, i64) -> i64 {
+block0(v0: i16, v1: i64, v2: i64):
+  v3 = iconst.i16 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i64 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxth w5, w0
+;   subs wzr, w5, #42
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
+
+function %f(i16, i128, i128) -> i128 {
+block0(v0: i16, v1: i128, v2: i128):
+  v3 = iconst.i16 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i128 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   uxth w8, w0
+;   subs wzr, w8, #42
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   csdb
+;   ret
+
+function %f(i32, i8, i8) -> i8 {
+block0(v0: i32, v1: i8, v2: i8):
+  v3 = iconst.i32 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i8 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs wzr, w0, #42
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
+
+function %f(i32, i16, i16) -> i16 {
+block0(v0: i32, v1: i16, v2: i16):
+  v3 = iconst.i32 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i16 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs wzr, w0, #42
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
+
+function %f(i32, i32, i32) -> i32 {
+block0(v0: i32, v1: i32, v2: i32):
+  v3 = iconst.i32 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i32 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs wzr, w0, #42
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
+
+function %f(i32, i64, i64) -> i64 {
+block0(v0: i32, v1: i64, v2: i64):
+  v3 = iconst.i32 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i64 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs wzr, w0, #42
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
+
+function %f(i32, i128, i128) -> i128 {
+block0(v0: i32, v1: i128, v2: i128):
+  v3 = iconst.i32 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i128 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs wzr, w0, #42
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   csdb
+;   ret
+
+function %f(i64, i8, i8) -> i8 {
+block0(v0: i64, v1: i8, v2: i8):
+  v3 = iconst.i64 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i8 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs xzr, x0, #42
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
+
+function %f(i64, i16, i16) -> i16 {
+block0(v0: i64, v1: i16, v2: i16):
+  v3 = iconst.i64 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i16 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs xzr, x0, #42
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
+
+function %f(i64, i32, i32) -> i32 {
+block0(v0: i64, v1: i32, v2: i32):
+  v3 = iconst.i64 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i32 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs xzr, x0, #42
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
+
+function %f(i64, i64, i64) -> i64 {
+block0(v0: i64, v1: i64, v2: i64):
+  v3 = iconst.i64 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i64 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs xzr, x0, #42
+;   csel x0, x1, x2, eq
+;   csdb
+;   ret
+
+function %f(i64, i128, i128) -> i128 {
+block0(v0: i64, v1: i128, v2: i128):
+  v3 = iconst.i64 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i128 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   subs xzr, x0, #42
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   csdb
+;   ret
+
+function %f(i128, i8, i8) -> i8 {
+block0(v0: i128, v1: i8, v2: i8):
+  v3 = iconst.i128 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i8 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   movz x6, #42
+;   movz x8, #0
+;   subs xzr, x0, x6
+;   ccmp x1, x8, #nzcv, eq
+;   csel x0, x2, x3, eq
+;   csdb
+;   ret
+
+function %f(i128, i16, i16) -> i16 {
+block0(v0: i128, v1: i16, v2: i16):
+  v3 = iconst.i128 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i16 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   movz x6, #42
+;   movz x8, #0
+;   subs xzr, x0, x6
+;   ccmp x1, x8, #nzcv, eq
+;   csel x0, x2, x3, eq
+;   csdb
+;   ret
+
+function %f(i128, i32, i32) -> i32 {
+block0(v0: i128, v1: i32, v2: i32):
+  v3 = iconst.i128 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i32 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   movz x6, #42
+;   movz x8, #0
+;   subs xzr, x0, x6
+;   ccmp x1, x8, #nzcv, eq
+;   csel x0, x2, x3, eq
+;   csdb
+;   ret
+
+function %f(i128, i64, i64) -> i64 {
+block0(v0: i128, v1: i64, v2: i64):
+  v3 = iconst.i128 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i64 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   movz x6, #42
+;   movz x8, #0
+;   subs xzr, x0, x6
+;   ccmp x1, x8, #nzcv, eq
+;   csel x0, x2, x3, eq
+;   csdb
+;   ret
+
+function %f(i128, i128, i128) -> i128 {
+block0(v0: i128, v1: i128, v2: i128):
+  v3 = iconst.i128 42
+  v4 = ifcmp v0, v3
+  v5 = selectif_spectre_guard.i128 eq v4, v1, v2
+  return v5
+}
+
+; block0:
+;   movz x9, #42
+;   movz x11, #0
+;   subs xzr, x0, x9
+;   ccmp x1, x11, #nzcv, eq
+;   csel x0, x2, x4, eq
+;   csel x1, x3, x5, eq
+;   csdb
+;   ret
+
 function %g(i8) -> b1 {
 block0(v0: i8):
   v3 = iconst.i8 42
@@ -25,8 +746,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   uxtb w4, w0
-;   subs wzr, w4, #42
+;   uxtb w3, w0
+;   subs wzr, w3, #42
 ;   cset x0, eq
 ;   ret
 
@@ -49,8 +770,8 @@ block0(v0: b1, v1: i8, v2: i8):
 }
 
 ; block0:
-;   and w6, w0, #1
-;   subs wzr, w6, wzr
+;   and w5, w0, #1
+;   subs wzr, w5, wzr
 ;   csel x0, x1, x2, ne
 ;   ret
 
@@ -74,8 +795,8 @@ block0(v0: b1, v1: i128, v2: i128):
 }
 
 ; block0:
-;   and w10, w0, #1
-;   subs wzr, w10, wzr
+;   and w8, w0, #1
+;   subs wzr, w8, wzr
 ;   csel x0, x2, x4, ne
 ;   csel x1, x3, x5, ne
 ;   ret

cranelift/filetests/filetests/isa/aarch64/heap_addr.clif

@@ -21,8 +21,8 @@ block0(v0: i64, v1: i32):
 ;   b.ls label1 ; b label2
 ; block1:
 ;   add x11, x0, x1, UXTW
-;   subs xzr, x9, x10
 ;   movz x12, #0
+;   subs xzr, x9, x10
 ;   csel x0, x12, x11, hi
 ;   csdb
 ;   ret
@@ -44,9 +44,9 @@ block0(v0: i64, v1: i32):
 ;   b.ls label1 ; b label2
 ; block1:
 ;   add x9, x0, x1, UXTW
+;   movz x8, #0
 ;   subs xzr, x7, #65536
-;   movz x10, #0
-;   csel x0, x10, x9, hi
+;   csel x0, x8, x9, hi
 ;   csdb
 ;   ret
 ; block2:

cranelift/filetests/filetests/isa/aarch64/traps.clif

@@ -17,6 +17,7 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
+;   adds x3, x0, x1
 ;   b.hs 8 ; udf
 ;   ret