Allow 64-bit vectors and implement for interpreter (#4509)

* Allow 64-bit vectors and implement for interpreter

The AArch64 backend already supports 64-bit vectors; this simply allows
instructions to make use of that.

Implemented support for 64-bit vectors within the interpreter to allow
interpret runtests to use them.

Copyright (c) 2022 Arm Limited

* Disable 64-bit SIMD `iaddpairwise` tests on s390x

Copyright (c) 2022 Arm Limited

cranelift/codegen/meta/src/shared/instructions.rs

@@ -3533,8 +3533,8 @@ pub(crate) fn define(
         "A SIMD vector type containing integer lanes 8, 16, or 32 bits wide.",
         TypeSetBuilder::new()
             .ints(8..32)
-            .simd_lanes(4..16)
-            .dynamic_simd_lanes(4..16)
+            .simd_lanes(2..16)
+            .dynamic_simd_lanes(2..16)
             .includes_scalars(false)
             .build(),
     );

cranelift/codegen/src/data_value.rs

@@ -26,6 +26,7 @@ pub enum DataValue {
     F32(Ieee32),
     F64(Ieee64),
     V128([u8; 16]),
+    V64([u8; 8]),
 }
 
 impl DataValue {
@@ -54,13 +55,14 @@ impl DataValue {
             DataValue::F32(_) => types::F32,
             DataValue::F64(_) => types::F64,
             DataValue::V128(_) => types::I8X16, // A default type.
+            DataValue::V64(_) => types::I8X8,   // A default type.
         }
     }
 
     /// Return true if the value is a vector (i.e. `DataValue::V128`).
     pub fn is_vector(&self) -> bool {
         match self {
-            DataValue::V128(_) => true,
+            DataValue::V128(_) | DataValue::V64(_) => true,
             _ => false,
         }
     }
@@ -90,6 +92,7 @@ impl DataValue {
             DataValue::F32(f) => dst[..4].copy_from_slice(&f.bits().to_ne_bytes()[..]),
             DataValue::F64(f) => dst[..8].copy_from_slice(&f.bits().to_ne_bytes()[..]),
             DataValue::V128(v) => dst[..16].copy_from_slice(&u128::from_le_bytes(*v).to_ne_bytes()),
+            DataValue::V64(v) => dst[..8].copy_from_slice(&u64::from_le_bytes(*v).to_ne_bytes()),
             _ => unimplemented!(),
         };
     }
@@ -119,8 +122,16 @@ impl DataValue {
                 let size = ty.bytes() as usize;
                 DataValue::B(src[..size].iter().any(|&i| i != 0))
             }
-            _ if ty.is_vector() && ty.bytes() == 16 => {
-                DataValue::V128(u128::from_ne_bytes(src[..16].try_into().unwrap()).to_le_bytes())
+            _ if ty.is_vector() => {
+                if ty.bytes() == 16 {
+                    DataValue::V128(
+                        u128::from_ne_bytes(src[..16].try_into().unwrap()).to_le_bytes(),
+                    )
+                } else if ty.bytes() == 8 {
+                    DataValue::V64(u64::from_ne_bytes(src[..8].try_into().unwrap()).to_le_bytes())
+                } else {
+                    unimplemented!()
+                }
             }
             _ => unimplemented!(),
         }
@@ -218,6 +229,7 @@ build_conversion_impl!(u128, U128, I128);
 build_conversion_impl!(Ieee32, F32, F32);
 build_conversion_impl!(Ieee64, F64, F64);
 build_conversion_impl!([u8; 16], V128, I8X16);
+build_conversion_impl!([u8; 8], V64, I8X8);
 impl From<Offset32> for DataValue {
     fn from(o: Offset32) -> Self {
         DataValue::from(Into::<i32>::into(o))
@@ -243,6 +255,7 @@ impl Display for DataValue {
             DataValue::F64(dv) => write!(f, "{}", dv),
             // Again, for syntax consistency, use ConstantData, which in this case displays as hex.
             DataValue::V128(dv) => write!(f, "{}", ConstantData::from(&dv[..])),
+            DataValue::V64(dv) => write!(f, "{}", ConstantData::from(&dv[..])),
         }
     }
 }

cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs

@@ -4035,6 +4035,18 @@ fn test_aarch64_binemit() {
         "fmul v2.2d, v0.2d, v5.2d",
     ));
 
+    insns.push((
+        Inst::VecRRR {
+            alu_op: VecALUOp::Addp,
+            rd: writable_vreg(16),
+            rn: vreg(12),
+            rm: vreg(1),
+            size: VectorSize::Size8x8,
+        },
+        "90BD210E",
+        "addp v16.8b, v12.8b, v1.8b",
+    ));
+
     insns.push((
         Inst::VecRRR {
             alu_op: VecALUOp::Addp,
@@ -4059,6 +4071,18 @@ fn test_aarch64_binemit() {
         "addp v8.4s, v12.4s, v14.4s",
     ));
 
+    insns.push((
+        Inst::VecRRR {
+            alu_op: VecALUOp::Addp,
+            rd: writable_vreg(8),
+            rn: vreg(12),
+            rm: vreg(14),
+            size: VectorSize::Size32x2,
+        },
+        "88BDAE0E",
+        "addp v8.2s, v12.2s, v14.2s",
+    ));
+
     insns.push((
         Inst::VecRRR {
             alu_op: VecALUOp::Zip1,