cranelift: Rename i{min,max} to s{min,max} (#5187)

This brings these instructions with our general naming convention
of signed instructions being prefixed with `s`.

cranelift/codegen/meta/src/shared/instructions.rs

@@ -416,7 +416,7 @@ fn define_simd_arithmetic(
 
     ig.push(
         Inst::new(
-            "imin",
+            "smin",
             r#"
         Signed integer minimum.
         "#,
@@ -440,7 +440,7 @@ fn define_simd_arithmetic(
 
     ig.push(
         Inst::new(
-            "imax",
+            "smax",
             r#"
         Signed integer maximum.
         "#,

cranelift/codegen/src/isa/aarch64/lower.isle

@@ -874,12 +874,12 @@
             (result Reg (msub $I64 div y64 x64)))
         result))
 
-;;; Rules for integer min/max: umin, imin, umax, imax ;;;;;;;;;;;;;;;;;;;;;;;;;
+;;; Rules for integer min/max: umin, smin, umax, smax ;;;;;;;;;;;;;;;;;;;;;;;;;
 
-(rule (lower (has_type ty @ (not_i64x2) (imin x y)))
+(rule (lower (has_type ty @ (not_i64x2) (smin x y)))
       (vec_rrr (VecALUOp.Smin) x y (vector_size ty)))
 
-(rule 1 (lower (has_type $I64X2 (imin x y)))
+(rule 1 (lower (has_type $I64X2 (smin x y)))
       (bsl $I64X2 (vec_rrr (VecALUOp.Cmgt) y x (VectorSize.Size64x2)) x y))
 
 (rule (lower (has_type ty @ (not_i64x2) (umin x y)))
@@ -888,10 +888,10 @@
 (rule 1 (lower (has_type $I64X2 (umin x y)))
       (bsl $I64X2 (vec_rrr (VecALUOp.Cmhi) y x (VectorSize.Size64x2)) x y))
 
-(rule (lower (has_type ty @ (not_i64x2) (imax x y)))
+(rule (lower (has_type ty @ (not_i64x2) (smax x y)))
       (vec_rrr (VecALUOp.Smax) x y (vector_size ty)))
 
-(rule 1 (lower (has_type $I64X2 (imax x y)))
+(rule 1 (lower (has_type $I64X2 (smax x y)))
       (bsl $I64X2 (vec_rrr (VecALUOp.Cmgt) x y (VectorSize.Size64x2)) x y))
 
 (rule (lower (has_type ty @ (not_i64x2) (umax x y)))

cranelift/codegen/src/isa/aarch64/lower_inst.rs

@@ -225,7 +225,7 @@ pub(crate) fn lower_insn_to_regs(
 
         Opcode::Iconcat => implemented_in_isle(ctx),
 
-        Opcode::Imax | Opcode::Umax | Opcode::Umin | Opcode::Imin => implemented_in_isle(ctx),
+        Opcode::Smax | Opcode::Umax | Opcode::Umin | Opcode::Smin => implemented_in_isle(ctx),
 
         Opcode::IaddPairwise => implemented_in_isle(ctx),
 

cranelift/codegen/src/isa/riscv64/inst.isle

@@ -367,9 +367,9 @@
 ))
 
 (type IntSelectOP (enum
-  (Imax)
+  (Smax)
   (Umax)
-  (Imin)
+  (Smin)
   (Umin)
 ))
 

cranelift/codegen/src/isa/riscv64/inst/args.rs

@@ -1493,7 +1493,7 @@ impl AtomicOP {
     }
 
     /// like extract but sign extend the value.
-    /// suitable for imax.
+    /// suitable for smax.
     pub(crate) fn extract_sext(
         rd: WritableReg,
         offset: Reg,
@@ -1594,9 +1594,9 @@ impl IntSelectOP {
     #[inline]
     pub(crate) fn from_ir_op(op: crate::ir::Opcode) -> Self {
         match op {
-            crate::ir::Opcode::Imax => Self::Imax,
+            crate::ir::Opcode::Smax => Self::Smax,
             crate::ir::Opcode::Umax => Self::Umax,
-            crate::ir::Opcode::Imin => Self::Imin,
+            crate::ir::Opcode::Smin => Self::Smin,
             crate::ir::Opcode::Umin => Self::Umin,
             _ => unreachable!(),
         }
@@ -1604,18 +1604,18 @@ impl IntSelectOP {
     #[inline]
     pub(crate) fn op_name(self) -> &'static str {
         match self {
-            IntSelectOP::Imax => "imax",
+            IntSelectOP::Smax => "smax",
             IntSelectOP::Umax => "umax",
-            IntSelectOP::Imin => "imin",
+            IntSelectOP::Smin => "smin",
             IntSelectOP::Umin => "umin",
         }
     }
     #[inline]
     pub(crate) fn to_int_cc(self) -> IntCC {
         match self {
-            IntSelectOP::Imax => IntCC::SignedGreaterThan,
+            IntSelectOP::Smax => IntCC::SignedGreaterThan,
             IntSelectOP::Umax => IntCC::UnsignedGreaterThan,
-            IntSelectOP::Imin => IntCC::SignedLessThan,
+            IntSelectOP::Smin => IntCC::SignedLessThan,
             IntSelectOP::Umin => IntCC::UnsignedLessThan,
         }
     }

cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs

@@ -2188,7 +2188,7 @@ fn riscv64_worst_case_instruction_size() {
     candidates.push(Inst::IntSelect {
         dst: vec![writable_a0(), writable_a0()],
         ty: I128,
-        op: IntSelectOP::Imax,
+        op: IntSelectOP::Smax,
         x: ValueRegs::two(x_reg(1), x_reg(2)),
         y: ValueRegs::two(x_reg(3), x_reg(4)),
     });

cranelift/codegen/src/isa/riscv64/lower.isle

@@ -635,15 +635,15 @@
       (t2 Reg (gen_move2 y $I64 $I64)))
     (value_regs t1 t2)))
 
-;;;;;  Rules for `imax`;;;;;;;;;
+;;;;;  Rules for `smax`;;;;;;;;;
 (rule
-  (lower (has_type ty (imax x y)))
+  (lower (has_type ty (smax x y)))
-  (gen_int_select ty (IntSelectOP.Imax) (ext_int_if_need $true x ty) (ext_int_if_need $true y ty)))
+  (gen_int_select ty (IntSelectOP.Smax) (ext_int_if_need $true x ty) (ext_int_if_need $true y ty)))
 
-;;;;;  Rules for `imin`;;;;;;;;;
+;;;;;  Rules for `smin`;;;;;;;;;
 (rule
-  (lower (has_type ty (imin x y)))
+  (lower (has_type ty (smin x y)))
-  (gen_int_select ty (IntSelectOP.Imin) (ext_int_if_need $true x ty) (ext_int_if_need $true y ty)))
+  (gen_int_select ty (IntSelectOP.Smin) (ext_int_if_need $true x ty) (ext_int_if_need $true y ty)))
 ;;;;;  Rules for `umax`;;;;;;;;;
 (rule
   (lower (has_type ty (umax x y)))

cranelift/codegen/src/isa/s390x/inst.isle

@@ -4132,7 +4132,7 @@
 (rule (vec_umax ty x y) (vec_rrr ty (vecop_umax ty) x y))
 
 
-;; Helpers for generating `imax` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Helpers for generating `smax` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (decl vecop_smax (Type) VecBinaryOp)
 (rule (vecop_smax $I8X16) (VecBinaryOp.SMax8x16))
@@ -4156,7 +4156,7 @@
 (rule (vec_umin ty x y) (vec_rrr ty (vecop_umin ty) x y))
 
 
-;; Helpers for generating `imin` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Helpers for generating `smin` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (decl vecop_smin (Type) VecBinaryOp)
 (rule (vecop_smin $I8X16) (VecBinaryOp.SMin8x16))

cranelift/codegen/src/isa/s390x/lower.isle

@@ -291,17 +291,17 @@
       (vec_umin ty x y))
 
 
-;;;; Rules for `imax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;; Rules for `smax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; Signed maximum of two vector registers.
-(rule (lower (has_type (ty_vec128 ty) (imax x y)))
+(rule (lower (has_type (ty_vec128 ty) (smax x y)))
       (vec_smax ty x y))
 
 
-;;;; Rules for `imin` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;; Rules for `smin` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; Signed minimum of two vector registers.
-(rule (lower (has_type (ty_vec128 ty) (imin x y)))
+(rule (lower (has_type (ty_vec128 ty) (smin x y)))
       (vec_smin ty x y))
 
 

cranelift/codegen/src/isa/s390x/lower.rs

@@ -58,9 +58,9 @@ impl LowerBackend for S390xBackend {
             | Opcode::UsubSat
             | Opcode::SsubSat
             | Opcode::IaddPairwise
-            | Opcode::Imin
+            | Opcode::Smin
             | Opcode::Umin
-            | Opcode::Imax
+            | Opcode::Smax
             | Opcode::Umax
             | Opcode::AvgRound
             | Opcode::Iabs

cranelift/codegen/src/isa/x64/lower.isle

@@ -1328,7 +1328,7 @@
 (rule (vec_insert_lane $F64X2 vec val 1)
       (x64_movlhps vec (reg_mem_to_xmm_mem val)))
 
-;;;; Rules for `imin`, `imax`, `umin`, `umax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;; Rules for `smin`, `smax`, `umin`, `umax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; `i64` and smaller.
 
@@ -1350,32 +1350,32 @@
 (rule -1 (lower (has_type (fits_in_64 ty) (umax x y)))
       (cmp_and_choose ty (CC.NB) x y))
 
-(rule -1 (lower (has_type (fits_in_64 ty) (imin x y)))
+(rule -1 (lower (has_type (fits_in_64 ty) (smin x y)))
       (cmp_and_choose ty (CC.L) x y))
 
-(rule -1 (lower (has_type (fits_in_64 ty) (imax x y)))
+(rule -1 (lower (has_type (fits_in_64 ty) (smax x y)))
       (cmp_and_choose ty (CC.NL) x y))
 
-;; SSE `imax`.
+;; SSE `smax`.
 
-(rule (lower (has_type $I8X16 (imax x y)))
+(rule (lower (has_type $I8X16 (smax x y)))
       (x64_pmaxsb x y))
 
-(rule (lower (has_type $I16X8 (imax x y)))
+(rule (lower (has_type $I16X8 (smax x y)))
       (x64_pmaxsw x y))
 
-(rule (lower (has_type $I32X4 (imax x y)))
+(rule (lower (has_type $I32X4 (smax x y)))
       (x64_pmaxsd x y))
 
-;; SSE `imin`.
+;; SSE `smin`.
 
-(rule (lower (has_type $I8X16 (imin x y)))
+(rule (lower (has_type $I8X16 (smin x y)))
       (x64_pminsb x y))
 
-(rule (lower (has_type $I16X8 (imin x y)))
+(rule (lower (has_type $I16X8 (smin x y)))
       (x64_pminsw x y))
 
-(rule (lower (has_type $I32X4 (imin x y)))
+(rule (lower (has_type $I32X4 (smin x y)))
       (x64_pminsd x y))
 
 ;; SSE `umax`.

cranelift/codegen/src/isa/x64/lower.rs

@@ -344,9 +344,9 @@ fn lower_insn_to_regs(
         | Opcode::Imul
         | Opcode::BandNot
         | Opcode::Iabs
-        | Opcode::Imax
+        | Opcode::Smax
         | Opcode::Umax
-        | Opcode::Imin
+        | Opcode::Smin
         | Opcode::Umin
         | Opcode::Bnot
         | Opcode::Bitselect

cranelift/filetests/filetests/isa/aarch64/simd-min-max.clif

@@ -4,7 +4,7 @@ target aarch64
 
 function %fn0(i8x8, i8x8) -> i8x8 {
 block0(v0: i8x8, v1: i8x8):
-  v2 = imin v0, v1
+  v2 = smin v0, v1
   return v2
 }
 
@@ -14,7 +14,7 @@ block0(v0: i8x8, v1: i8x8):
 
 function %fn1(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
-  v2 = imin v0, v1
+  v2 = smin v0, v1
   return v2
 }
 
@@ -24,7 +24,7 @@ block0(v0: i8x16, v1: i8x16):
 
 function %fn2(i16x4, i16x4) -> i16x4 {
 block0(v0: i16x4, v1: i16x4):
-  v2 = imin v0, v1
+  v2 = smin v0, v1
   return v2
 }
 
@@ -34,7 +34,7 @@ block0(v0: i16x4, v1: i16x4):
 
 function %fn3(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
-  v2 = imin v0, v1
+  v2 = smin v0, v1
   return v2
 }
 
@@ -44,7 +44,7 @@ block0(v0: i16x8, v1: i16x8):
 
 function %fn4(i32x2, i32x2) -> i32x2 {
 block0(v0: i32x2, v1: i32x2):
-  v2 = imin v0, v1
+  v2 = smin v0, v1
   return v2
 }
 
@@ -54,7 +54,7 @@ block0(v0: i32x2, v1: i32x2):
 
 function %fn5(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
-  v2 = imin v0, v1
+  v2 = smin v0, v1
   return v2
 }
 
@@ -124,7 +124,7 @@ block0(v0: i32x4, v1: i32x4):
 
 function %fn12(i8x8, i8x8) -> i8x8 {
 block0(v0: i8x8, v1: i8x8):
-  v2 = imax v0, v1
+  v2 = smax v0, v1
   return v2
 }
 
@@ -134,7 +134,7 @@ block0(v0: i8x8, v1: i8x8):
 
 function %fn13(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
-  v2 = imax v0, v1
+  v2 = smax v0, v1
   return v2
 }
 
@@ -144,7 +144,7 @@ block0(v0: i8x16, v1: i8x16):
 
 function %fn14(i16x4, i16x4) -> i16x4 {
 block0(v0: i16x4, v1: i16x4):
-  v2 = imax v0, v1
+  v2 = smax v0, v1
   return v2
 }
 
@@ -154,7 +154,7 @@ block0(v0: i16x4, v1: i16x4):
 
 function %fn15(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
-  v2 = imax v0, v1
+  v2 = smax v0, v1
   return v2
 }
 
@@ -164,7 +164,7 @@ block0(v0: i16x8, v1: i16x8):
 
 function %fn16(i32x2, i32x2) -> i32x2 {
 block0(v0: i32x2, v1: i32x2):
-  v2 = imax v0, v1
+  v2 = smax v0, v1
   return v2
 }
 
@@ -174,7 +174,7 @@ block0(v0: i32x2, v1: i32x2):
 
 function %fn17(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
-  v2 = imax v0, v1
+  v2 = smax v0, v1
   return v2
 }
 

cranelift/filetests/filetests/isa/s390x/vec-arithmetic.clif

@@ -241,9 +241,9 @@ block0(v0: i8x16, v1: i8x16):
 ;   vmnlb %v24, %v24, %v25
 ;   br %r14
 
-function %imax_i64x2(i64x2, i64x2) -> i64x2 {
+function %smax_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
-  v2 = imax.i64x2 v0, v1
+  v2 = smax.i64x2 v0, v1
   return v2
 }
 
@@ -251,9 +251,9 @@ block0(v0: i64x2, v1: i64x2):
 ;   vmxg %v24, %v24, %v25
 ;   br %r14
 
-function %imax_i32x4(i32x4, i32x4) -> i32x4 {
+function %smax_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
-  v2 = imax.i32x4 v0, v1
+  v2 = smax.i32x4 v0, v1
   return v2
 }
 
@@ -261,9 +261,9 @@ block0(v0: i32x4, v1: i32x4):
 ;   vmxf %v24, %v24, %v25
 ;   br %r14
 
-function %imax_i16x8(i16x8, i16x8) -> i16x8 {
+function %smax_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
-  v2 = imax.i16x8 v0, v1
+  v2 = smax.i16x8 v0, v1
   return v2
 }
 
@@ -271,9 +271,9 @@ block0(v0: i16x8, v1: i16x8):
 ;   vmxh %v24, %v24, %v25
 ;   br %r14
 
-function %imax_i8x16(i8x16, i8x16) -> i8x16 {
+function %smax_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
-  v2 = imax.i8x16 v0, v1
+  v2 = smax.i8x16 v0, v1
   return v2
 }
 
@@ -281,9 +281,9 @@ block0(v0: i8x16, v1: i8x16):
 ;   vmxb %v24, %v24, %v25
 ;   br %r14
 
-function %imin_i64x2(i64x2, i64x2) -> i64x2 {
+function %smin_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
-  v2 = imin.i64x2 v0, v1
+  v2 = smin.i64x2 v0, v1
   return v2
 }
 
@@ -291,9 +291,9 @@ block0(v0: i64x2, v1: i64x2):
 ;   vmng %v24, %v24, %v25
 ;   br %r14
 
-function %imin_i32x4(i32x4, i32x4) -> i32x4 {
+function %smin_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
-  v2 = imin.i32x4 v0, v1
+  v2 = smin.i32x4 v0, v1
   return v2
 }
 
@@ -301,9 +301,9 @@ block0(v0: i32x4, v1: i32x4):
 ;   vmnf %v24, %v24, %v25
 ;   br %r14
 
-function %imin_i16x8(i16x8, i16x8) -> i16x8 {
+function %smin_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
-  v2 = imin.i16x8 v0, v1
+  v2 = smin.i16x8 v0, v1
   return v2
 }
 
@@ -311,9 +311,9 @@ block0(v0: i16x8, v1: i16x8):
 ;   vmnh %v24, %v24, %v25
 ;   br %r14
 
-function %imin_i8x16(i8x16, i8x16) -> i8x16 {
+function %smin_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
-  v2 = imin.i8x16 v0, v1
+  v2 = smin.i8x16 v0, v1
   return v2
 }
 

cranelift/filetests/filetests/runtests/integer-minmax.clif

@@ -6,18 +6,18 @@ target x86_64
 target riscv64
 
 
-; sort three signed i8s with imin and imax only
+; sort three signed i8s with smin and smax only
 function %isort3(i8, i8, i8) -> i8, i8, i8 {
 block0(v0: i8, v1: i8, v2: i8):
-    v3 = imin.i8 v0, v1
+    v3 = smin.i8 v0, v1
-    v4 = imin.i8 v1, v2
+    v4 = smin.i8 v1, v2
-    v5 = imin.i8 v2, v0
+    v5 = smin.i8 v2, v0
-    v6 = imin.i8 v3, v4 ; low
+    v6 = smin.i8 v3, v4 ; low
-    v7 = imax.i8 v0, v1
+    v7 = smax.i8 v0, v1
-    v8 = imax.i8 v1, v2
+    v8 = smax.i8 v1, v2
-    v9 = imax.i8 v7, v8 ; high
+    v9 = smax.i8 v7, v8 ; high
-    v10 = imax.i8 v3, v4
+    v10 = smax.i8 v3, v4
-    v11 = imax.i8 v10, v5 ; mid = max of min of all pairs
+    v11 = smax.i8 v10, v5 ; mid = max of min of all pairs
     return v6, v11, v9
 }
 ; run: %isort3(1, 2, 3) == [1, 2, 3]
@@ -33,65 +33,65 @@ block0(v0: i8, v1: i8, v2: i8):
 ; run: %isort3(5, 4, 4) == [4, 4, 5]
 
 
-function %imin_max_i8(i8, i8) -> i8, i8 {
+function %smin_max_i8(i8, i8) -> i8, i8 {
 block0(v0: i8, v1: i8):
-    v2 = imin.i8 v0, v1
+    v2 = smin.i8 v0, v1
-    v3 = imax.i8 v0, v1
+    v3 = smax.i8 v0, v1
     return v2, v3
 }
-; run: %imin_max_i8(127, -128) == [-128, 127]
+; run: %smin_max_i8(127, -128) == [-128, 127]
-; run: %imin_max_i8(-128, 127) == [-128, 127]
+; run: %smin_max_i8(-128, 127) == [-128, 127]
-; run: %imin_max_i8(-1, 0) == [-1, 0]
+; run: %smin_max_i8(-1, 0) == [-1, 0]
-; run: %imin_max_i8(1, -1) == [-1, 1]
+; run: %smin_max_i8(1, -1) == [-1, 1]
-; run: %imin_max_i8(1, 2) == [1, 2]
+; run: %smin_max_i8(1, 2) == [1, 2]
-; run: %imin_max_i8(2, 1) == [1, 2]
+; run: %smin_max_i8(2, 1) == [1, 2]
-; run: %imin_max_i8(2, 2) == [2, 2]
+; run: %smin_max_i8(2, 2) == [2, 2]
-; run: %imin_max_i8(0x7f, 0x80) == [0x80, 0x7f]
+; run: %smin_max_i8(0x7f, 0x80) == [0x80, 0x7f]
 
-function %imin_max_i16(i16, i16) -> i16, i16 {
+function %smin_max_i16(i16, i16) -> i16, i16 {
 block0(v0: i16, v1: i16):
-    v2 = imin.i16 v0, v1
+    v2 = smin.i16 v0, v1
-    v3 = imax.i16 v0, v1
+    v3 = smax.i16 v0, v1
     return v2, v3
 }
-; run: %imin_max_i16(32767, -32768) == [-32768, 32767]
+; run: %smin_max_i16(32767, -32768) == [-32768, 32767]
-; run: %imin_max_i16(-32768, 32767) == [-32768, 32767]
+; run: %smin_max_i16(-32768, 32767) == [-32768, 32767]
-; run: %imin_max_i16(-1, 0) == [-1, 0]
+; run: %smin_max_i16(-1, 0) == [-1, 0]
-; run: %imin_max_i16(1, -1) == [-1, 1]
+; run: %smin_max_i16(1, -1) == [-1, 1]
-; run: %imin_max_i16(1, 2) == [1, 2]
+; run: %smin_max_i16(1, 2) == [1, 2]
-; run: %imin_max_i16(2, 1) == [1, 2]
+; run: %smin_max_i16(2, 1) == [1, 2]
-; run: %imin_max_i16(2, 2) == [2, 2]
+; run: %smin_max_i16(2, 2) == [2, 2]
-; run: %imin_max_i16(0x7f, 0x80) == [0x7f, 0x80]
+; run: %smin_max_i16(0x7f, 0x80) == [0x7f, 0x80]
-; run: %imin_max_i16(0x7fff, 0x8000) == [0x8000, 0x7fff]
+; run: %smin_max_i16(0x7fff, 0x8000) == [0x8000, 0x7fff]
 
-function %imin_max_i32(i32, i32) -> i32, i32 {
+function %smin_max_i32(i32, i32) -> i32, i32 {
 block0(v0: i32, v1: i32):
-    v2 = imin.i32 v0, v1
+    v2 = smin.i32 v0, v1
-    v3 = imax.i32 v0, v1
+    v3 = smax.i32 v0, v1
     return v2, v3
 }
-; run: %imin_max_i32(-1, 0) == [-1, 0]
+; run: %smin_max_i32(-1, 0) == [-1, 0]
-; run: %imin_max_i32(1, -1) == [-1, 1]
+; run: %smin_max_i32(1, -1) == [-1, 1]
-; run: %imin_max_i32(1, 2) == [1, 2]
+; run: %smin_max_i32(1, 2) == [1, 2]
-; run: %imin_max_i32(2, 1) == [1, 2]
+; run: %smin_max_i32(2, 1) == [1, 2]
-; run: %imin_max_i32(0x7f, 0x80) == [0x7f, 0x80]
+; run: %smin_max_i32(0x7f, 0x80) == [0x7f, 0x80]
-; run: %imin_max_i32(0x7fff, 0x8000) == [0x7fff, 0x8000]
+; run: %smin_max_i32(0x7fff, 0x8000) == [0x7fff, 0x8000]
-; run: %imin_max_i32(0x7fffffff, 0x80000000) == [0x80000000, 0x7fffffff]
+; run: %smin_max_i32(0x7fffffff, 0x80000000) == [0x80000000, 0x7fffffff]
 
-function %imin_max_i64(i64, i64) -> i64, i64 {
+function %smin_max_i64(i64, i64) -> i64, i64 {
 block0(v0: i64, v1: i64):
-    v2 = imin.i64 v0, v1
+    v2 = smin.i64 v0, v1
-    v3 = imax.i64 v0, v1
+    v3 = smax.i64 v0, v1
     return v2, v3
 }
-; run: %imin_max_i64(-1, 0) == [-1, 0]
+; run: %smin_max_i64(-1, 0) == [-1, 0]
-; run: %imin_max_i64(1, -1) == [-1, 1]
+; run: %smin_max_i64(1, -1) == [-1, 1]
-; run: %imin_max_i64(1, 2) == [1, 2]
+; run: %smin_max_i64(1, 2) == [1, 2]
-; run: %imin_max_i64(2, 1) == [1, 2]
+; run: %smin_max_i64(2, 1) == [1, 2]
-; run: %imin_max_i64(0x7f, 0x80) == [0x7f, 0x80]
+; run: %smin_max_i64(0x7f, 0x80) == [0x7f, 0x80]
-; run: %imin_max_i64(0x7fff, 0x8000) == [0x7fff, 0x8000]
+; run: %smin_max_i64(0x7fff, 0x8000) == [0x7fff, 0x8000]
-; run: %imin_max_i64(0x7fffffff, 0x80000000) == [0x7fffffff, 0x80000000]
+; run: %smin_max_i64(0x7fffffff, 0x80000000) == [0x7fffffff, 0x80000000]
-; run: %imin_max_i64(0x7fffffffffffffff, 0x8000000000000000) == [0x8000000000000000, 0x7fffffffffffffff]
+; run: %smin_max_i64(0x7fffffffffffffff, 0x8000000000000000) == [0x8000000000000000, 0x7fffffffffffffff]
 
 function %umin_max_i8(i8, i8) -> i8, i8 {
 block0(v0: i8, v1: i8):

cranelift/filetests/filetests/runtests/simd-min-max-aarch64.clif

@@ -2,23 +2,23 @@ test run
 test interpret
 target aarch64
 
-function %imin_i64x2(i64x2, i64x2) -> i64x2 {
+function %smin_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
-  v2 = imin v0, v1
+  v2 = smin v0, v1
   return v2
 }
 
-; run: %imin_i64x2([0xC00FFFEE 0xBADAB00F], [0x98763210 0x43216789]) == [ 0x98763210 0x43216789 ]
+; run: %smin_i64x2([0xC00FFFEE 0xBADAB00F], [0x98763210 0x43216789]) == [ 0x98763210 0x43216789 ]
-; run: %imin_i64x2([0x80000000C00FFFEE 0xBADAB00F], [0x98763210 0x43216789]) == [ 0x80000000C00FFFEE 0x43216789 ]
+; run: %smin_i64x2([0x80000000C00FFFEE 0xBADAB00F], [0x98763210 0x43216789]) == [ 0x80000000C00FFFEE 0x43216789 ]
 
-function %imax_i64x2(i64x2, i64x2) -> i64x2 {
+function %smax_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):
-  v2 = imax v0, v1
+  v2 = smax v0, v1
   return v2
 }
 
-; run: %imax_i64x2([0xC00FFFEE 0xBADAB00F], [0x98763210 0x43216789]) == [ 0xC00FFFEE 0xBADAB00F ]
+; run: %smax_i64x2([0xC00FFFEE 0xBADAB00F], [0x98763210 0x43216789]) == [ 0xC00FFFEE 0xBADAB00F ]
-; run: %imax_i64x2([0xC00FFFEE 0x80000000BADAB00F], [0x98763210 0x43216789]) == [ 0xC00FFFEE 0x43216789 ]
+; run: %smax_i64x2([0xC00FFFEE 0x80000000BADAB00F], [0x98763210 0x43216789]) == [ 0xC00FFFEE 0x43216789 ]
 
 function %umin_i64x2(i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2):

cranelift/filetests/filetests/runtests/simd-min-max.clif

@@ -4,31 +4,31 @@ target aarch64
 target x86_64
 target s390x
 
-function %imin_i8x16(i8x16, i8x16) -> i8x16 {
+function %smin_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
-  v2 = imin v0, v1
+  v2 = smin v0, v1
   return v2
 }
 
-; run: %imin_i8x16([0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f], [0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f ]) == [ 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f ]
+; run: %smin_i8x16([0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f], [0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f ]) == [ 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f ]
 
-; run: %imin_i8x16([0x90 0x01 0x92 0x03 0x94 0x05 0x96 0x07 0x98 0x09 0x9a 0x0b 0x9c 0x0d 0x9e 0x0f], [0x10 0x91 0x12 0x93 0x14 0x95 0x16 0x97 0x18 0x99 0x1a 0x9b 0x1c 0x9d 0x1e 0x9f ]) == [ 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f ]
+; run: %smin_i8x16([0x90 0x01 0x92 0x03 0x94 0x05 0x96 0x07 0x98 0x09 0x9a 0x0b 0x9c 0x0d 0x9e 0x0f], [0x10 0x91 0x12 0x93 0x14 0x95 0x16 0x97 0x18 0x99 0x1a 0x9b 0x1c 0x9d 0x1e 0x9f ]) == [ 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f ]
 
-function %imin_i16x8(i16x8, i16x8) -> i16x8 {
+function %smin_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
-  v2 = imin v0, v1
+  v2 = smin v0, v1
   return v2
 }
 
-; run: %imin_i16x8([0x1234 0x5678 0x9876 0x5432 0x7654 0x1234 0x4567 0x3456 ], [ 0x4567 0x1234 0x6789 0x0987 0x0123 0x3210 0x7890 0x3456 ]) == [ 0x1234 0x1234 0x9876 0x0987 0x0123 0x1234 0x4567 0x3456 ]
+; run: %smin_i16x8([0x1234 0x5678 0x9876 0x5432 0x7654 0x1234 0x4567 0x3456 ], [ 0x4567 0x1234 0x6789 0x0987 0x0123 0x3210 0x7890 0x3456 ]) == [ 0x1234 0x1234 0x9876 0x0987 0x0123 0x1234 0x4567 0x3456 ]
 
-function %imin_i32x4(i32x4, i32x4) -> i32x4 {
+function %smin_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
-  v2 = imin v0, v1
+  v2 = smin v0, v1
   return v2
 }
 
-; run: %imin_i32x4([0xBAADF00D 0xDEADBEEF 0xC00FFFEE 0xBADAB00F], [0xCA11ACAB 0x12349876 0x98763210 0x43216789]) == [ 0xBAADF00D 0xDEADBEEF 0x98763210 0xBADAB00F ]
+; run: %smin_i32x4([0xBAADF00D 0xDEADBEEF 0xC00FFFEE 0xBADAB00F], [0xCA11ACAB 0x12349876 0x98763210 0x43216789]) == [ 0xBAADF00D 0xDEADBEEF 0x98763210 0xBADAB00F ]
 
 function %umin_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
@@ -56,31 +56,31 @@ block0(v0: i32x4, v1: i32x4):
 
 ; run: %umin_i32x4([0xBAADF00D 0xDEADBEEF 0xC00FFFEE 0xBADAB00F], [0xCA11ACAB 0x12349876 0x98763210 0x43216789]) == [ 0xBAADF00D 0x12349876 0x98763210 0x43216789 ]
 
-function %imax_i8x16(i8x16, i8x16) -> i8x16 {
+function %smax_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):
-  v2 = imax v0, v1
+  v2 = smax v0, v1
   return v2
 }
 
-; run: %imax_i8x16([0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f], [0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f ]) == [ 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f ]
+; run: %smax_i8x16([0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f], [0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f ]) == [ 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f ]
 
-; run: %imax_i8x16([0x90 0x01 0x92 0x03 0x94 0x05 0x96 0x07 0x98 0x09 0x9a 0x0b 0x9c 0x0d 0x9e 0x0f], [0x10 0x91 0x12 0x93 0x14 0x95 0x16 0x97 0x18 0x99 0x1a 0x9b 0x1c 0x9d 0x1e 0x9f ]) == [ 0x10 0x01 0x12 0x03 0x14 0x05 0x16 0x07 0x18 0x09 0x1a 0x0b 0x1c 0x0d 0x1e 0x0f ]
+; run: %smax_i8x16([0x90 0x01 0x92 0x03 0x94 0x05 0x96 0x07 0x98 0x09 0x9a 0x0b 0x9c 0x0d 0x9e 0x0f], [0x10 0x91 0x12 0x93 0x14 0x95 0x16 0x97 0x18 0x99 0x1a 0x9b 0x1c 0x9d 0x1e 0x9f ]) == [ 0x10 0x01 0x12 0x03 0x14 0x05 0x16 0x07 0x18 0x09 0x1a 0x0b 0x1c 0x0d 0x1e 0x0f ]
 
-function %imax_i16x8(i16x8, i16x8) -> i16x8 {
+function %smax_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):
-  v2 = imax v0, v1
+  v2 = smax v0, v1
   return v2
 }
 
-; run: %imax_i16x8([0x1234 0x5678 0x9876 0x5432 0x7654 0x1234 0x4567 0x3456 ], [ 0x4567 0x1234 0x6789 0x0987 0x0123 0x3210 0x7890 0x3456 ]) == [ 0x4567 0x5678 0x6789 0x5432 0x7654 0x3210 0x7890 0x3456 ]
+; run: %smax_i16x8([0x1234 0x5678 0x9876 0x5432 0x7654 0x1234 0x4567 0x3456 ], [ 0x4567 0x1234 0x6789 0x0987 0x0123 0x3210 0x7890 0x3456 ]) == [ 0x4567 0x5678 0x6789 0x5432 0x7654 0x3210 0x7890 0x3456 ]
 
-function %imax_i32x4(i32x4, i32x4) -> i32x4 {
+function %smax_i32x4(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
-  v2 = imax v0, v1
+  v2 = smax v0, v1
   return v2
 }
 
-; run: %imax_i32x4([0xBAADF00D 0xDEADBEEF 0xC00FFFEE 0xBADAB00F], [0xCA11ACAB 0x12349876 0x98763210 0x43216789]) == [ 0xCA11ACAB 0x12349876 0xC00FFFEE 0x43216789 ]
+; run: %smax_i32x4([0xBAADF00D 0xDEADBEEF 0xC00FFFEE 0xBADAB00F], [0xCA11ACAB 0x12349876 0x98763210 0x43216789]) == [ 0xCA11ACAB 0x12349876 0xC00FFFEE 0x43216789 ]
 
 function %umax_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):

cranelift/fuzzgen/src/function_generator.rs

@@ -283,20 +283,20 @@ const OPCODE_SIGNATURES: &'static [(
     (Opcode::Ineg, &[I32, I32], &[I32], insert_opcode),
     (Opcode::Ineg, &[I64, I64], &[I64], insert_opcode),
     (Opcode::Ineg, &[I128, I128], &[I128], insert_opcode),
-    // Imin
+    // Smin
-    // imin not implemented in some backends:
+    // smin not implemented in some backends:
     //   x64: https://github.com/bytecodealliance/wasmtime/issues/3370
     //   aarch64: https://github.com/bytecodealliance/wasmtime/issues/4313
     #[cfg(not(target_arch = "aarch64"))]
-    (Opcode::Imin, &[I8, I8], &[I8], insert_opcode),
+    (Opcode::Smin, &[I8, I8], &[I8], insert_opcode),
     #[cfg(not(target_arch = "aarch64"))]
-    (Opcode::Imin, &[I16, I16], &[I16], insert_opcode),
+    (Opcode::Smin, &[I16, I16], &[I16], insert_opcode),
     #[cfg(not(target_arch = "aarch64"))]
-    (Opcode::Imin, &[I32, I32], &[I32], insert_opcode),
+    (Opcode::Smin, &[I32, I32], &[I32], insert_opcode),
     #[cfg(not(target_arch = "aarch64"))]
-    (Opcode::Imin, &[I64, I64], &[I64], insert_opcode),
+    (Opcode::Smin, &[I64, I64], &[I64], insert_opcode),
     #[cfg(not(any(target_arch = "x86_64", target_arch = "aarch64")))]
-    (Opcode::Imin, &[I128, I128], &[I128], insert_opcode),
+    (Opcode::Smin, &[I128, I128], &[I128], insert_opcode),
     // Umin
     // umin not implemented in some backends:
     //   x64: https://github.com/bytecodealliance/wasmtime/issues/3370
@@ -311,20 +311,20 @@ const OPCODE_SIGNATURES: &'static [(
     (Opcode::Umin, &[I64, I64], &[I64], insert_opcode),
     #[cfg(not(any(target_arch = "x86_64", target_arch = "aarch64")))]
     (Opcode::Umin, &[I128, I128], &[I128], insert_opcode),
-    // Imax
+    // Smax
-    // imax not implemented in some backends:
+    // smax not implemented in some backends:
     //   x64: https://github.com/bytecodealliance/wasmtime/issues/3370
     //   aarch64: https://github.com/bytecodealliance/wasmtime/issues/4313
     #[cfg(not(target_arch = "aarch64"))]
-    (Opcode::Imax, &[I8, I8], &[I8], insert_opcode),
+    (Opcode::Smax, &[I8, I8], &[I8], insert_opcode),
     #[cfg(not(target_arch = "aarch64"))]
-    (Opcode::Imax, &[I16, I16], &[I16], insert_opcode),
+    (Opcode::Smax, &[I16, I16], &[I16], insert_opcode),
     #[cfg(not(target_arch = "aarch64"))]
-    (Opcode::Imax, &[I32, I32], &[I32], insert_opcode),
+    (Opcode::Smax, &[I32, I32], &[I32], insert_opcode),
     #[cfg(not(target_arch = "aarch64"))]
-    (Opcode::Imax, &[I64, I64], &[I64], insert_opcode),
+    (Opcode::Smax, &[I64, I64], &[I64], insert_opcode),
     #[cfg(not(any(target_arch = "x86_64", target_arch = "aarch64")))]
-    (Opcode::Imax, &[I128, I128], &[I128], insert_opcode),
+    (Opcode::Smax, &[I128, I128], &[I128], insert_opcode),
     // Umax
     // umax not implemented in some backends:
     //   x64: https://github.com/bytecodealliance/wasmtime/issues/3370

cranelift/interpreter/src/step.rs

@@ -589,7 +589,7 @@ where
             }
             ControlFlow::Continue
         }
-        Opcode::Imin => {
+        Opcode::Smin => {
             if ctrl_ty.is_vector() {
                 let icmp = icmp(ctrl_ty, IntCC::SignedGreaterThan, &arg(1)?, &arg(0)?)?;
                 assign(vselect(&icmp, &arg(0)?, &arg(1)?, ctrl_ty)?)
@@ -612,7 +612,7 @@ where
                 )
             }
         }
-        Opcode::Imax => {
+        Opcode::Smax => {
             if ctrl_ty.is_vector() {
                 let icmp = icmp(ctrl_ty, IntCC::SignedGreaterThan, &arg(0)?, &arg(1)?)?;
                 assign(vselect(&icmp, &arg(0)?, &arg(1)?, ctrl_ty)?)

cranelift/wasm/src/code_translator.rs

@@ -1570,7 +1570,7 @@ pub fn translate_operator<FE: FuncEnvironment + ?Sized>(
         }
         Operator::I8x16MinS | Operator::I16x8MinS | Operator::I32x4MinS => {
             let (a, b) = pop2_with_bitcast(state, type_of(op), builder);
-            state.push1(builder.ins().imin(a, b))
+            state.push1(builder.ins().smin(a, b))
         }
         Operator::I8x16MinU | Operator::I16x8MinU | Operator::I32x4MinU => {
             let (a, b) = pop2_with_bitcast(state, type_of(op), builder);
@@ -1578,7 +1578,7 @@ pub fn translate_operator<FE: FuncEnvironment + ?Sized>(
         }
         Operator::I8x16MaxS | Operator::I16x8MaxS | Operator::I32x4MaxS => {
             let (a, b) = pop2_with_bitcast(state, type_of(op), builder);
-            state.push1(builder.ins().imax(a, b))
+            state.push1(builder.ins().smax(a, b))
         }
         Operator::I8x16MaxU | Operator::I16x8MaxU | Operator::I32x4MaxU => {
             let (a, b) = pop2_with_bitcast(state, type_of(op), builder);