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cranelift: Rename i{min,max} to s{min,max} (#5187)

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This brings these instructions with our general naming convention
of signed instructions being prefixed with `s`.
This commit is contained in:
Afonso Bordado
2022-11-03 18:20:33 +00:00
committed by GitHub
parent 2c69b94744
commit 3ef30b5b67
20 changed files with 173 additions and 173 deletions
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4
cranelift/codegen/meta/src/shared/instructions.rs
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@@ -416,7 +416,7 @@ fn define_simd_arithmetic(
ig.push(
Inst::new(
"imin",
"smin",
r#"
Signed integer minimum.
"#,
@@ -440,7 +440,7 @@ fn define_simd_arithmetic(
ig.push(
Inst::new(
"imax",
"smax",
r#"
Signed integer maximum.
"#,

10
cranelift/codegen/src/isa/aarch64/lower.isle
View File

@@ -874,12 +874,12 @@
(result Reg (msub $I64 div y64 x64)))
result))
;;; Rules for integer min/max: umin, imin, umax, imax ;;;;;;;;;;;;;;;;;;;;;;;;;
;;; Rules for integer min/max: umin, smin, umax, smax ;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty @ (not_i64x2) (imin x y)))
(rule (lower (has_type ty @ (not_i64x2) (smin x y)))
(vec_rrr (VecALUOp.Smin) x y (vector_size ty)))
(rule 1 (lower (has_type $I64X2 (imin x y)))
(rule 1 (lower (has_type $I64X2 (smin x y)))
(bsl $I64X2 (vec_rrr (VecALUOp.Cmgt) y x (VectorSize.Size64x2)) x y))
(rule (lower (has_type ty @ (not_i64x2) (umin x y)))
@@ -888,10 +888,10 @@
(rule 1 (lower (has_type $I64X2 (umin x y)))
(bsl $I64X2 (vec_rrr (VecALUOp.Cmhi) y x (VectorSize.Size64x2)) x y))
(rule (lower (has_type ty @ (not_i64x2) (imax x y)))
(rule (lower (has_type ty @ (not_i64x2) (smax x y)))
(vec_rrr (VecALUOp.Smax) x y (vector_size ty)))
(rule 1 (lower (has_type $I64X2 (imax x y)))
(rule 1 (lower (has_type $I64X2 (smax x y)))
(bsl $I64X2 (vec_rrr (VecALUOp.Cmgt) x y (VectorSize.Size64x2)) x y))
(rule (lower (has_type ty @ (not_i64x2) (umax x y)))

2
cranelift/codegen/src/isa/aarch64/lower_inst.rs
View File

@@ -225,7 +225,7 @@ pub(crate) fn lower_insn_to_regs(
Opcode::Iconcat => implemented_in_isle(ctx),
Opcode::Imax | Opcode::Umax | Opcode::Umin | Opcode::Imin => implemented_in_isle(ctx),
Opcode::Smax | Opcode::Umax | Opcode::Umin | Opcode::Smin => implemented_in_isle(ctx),
Opcode::IaddPairwise => implemented_in_isle(ctx),

4
cranelift/codegen/src/isa/riscv64/inst.isle
View File

@@ -367,9 +367,9 @@
))
(type IntSelectOP (enum
(Imax)
(Smax)
(Umax)
(Imin)
(Smin)
(Umin)
))

14
cranelift/codegen/src/isa/riscv64/inst/args.rs
View File

@@ -1493,7 +1493,7 @@ impl AtomicOP {
}
/// like extract but sign extend the value.
/// suitable for imax.
/// suitable for smax.
pub(crate) fn extract_sext(
rd: WritableReg,
offset: Reg,
@@ -1594,9 +1594,9 @@ impl IntSelectOP {
#[inline]
pub(crate) fn from_ir_op(op: crate::ir::Opcode) -> Self {
match op {
crate::ir::Opcode::Imax => Self::Imax,
crate::ir::Opcode::Smax => Self::Smax,
crate::ir::Opcode::Umax => Self::Umax,
crate::ir::Opcode::Imin => Self::Imin,
crate::ir::Opcode::Smin => Self::Smin,
crate::ir::Opcode::Umin => Self::Umin,
_ => unreachable!(),
}
@@ -1604,18 +1604,18 @@ impl IntSelectOP {
#[inline]
pub(crate) fn op_name(self) -> &'static str {
match self {
IntSelectOP::Imax => "imax",
IntSelectOP::Smax => "smax",
IntSelectOP::Umax => "umax",
IntSelectOP::Imin => "imin",
IntSelectOP::Smin => "smin",
IntSelectOP::Umin => "umin",
}
}
#[inline]
pub(crate) fn to_int_cc(self) -> IntCC {
match self {
IntSelectOP::Imax => IntCC::SignedGreaterThan,
IntSelectOP::Smax => IntCC::SignedGreaterThan,
IntSelectOP::Umax => IntCC::UnsignedGreaterThan,
IntSelectOP::Imin => IntCC::SignedLessThan,
IntSelectOP::Smin => IntCC::SignedLessThan,
IntSelectOP::Umin => IntCC::UnsignedLessThan,
}
}

2
cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs
View File

@@ -2188,7 +2188,7 @@ fn riscv64_worst_case_instruction_size() {
candidates.push(Inst::IntSelect {
dst: vec![writable_a0(), writable_a0()],
ty: I128,
op: IntSelectOP::Imax,
op: IntSelectOP::Smax,
x: ValueRegs::two(x_reg(1), x_reg(2)),
y: ValueRegs::two(x_reg(3), x_reg(4)),
});

12
cranelift/codegen/src/isa/riscv64/lower.isle
View File

@@ -635,15 +635,15 @@
(t2 Reg (gen_move2 y $I64 $I64)))
(value_regs t1 t2)))
;;;;; Rules for `imax`;;;;;;;;;
;;;;; Rules for `smax`;;;;;;;;;
(rule
(lower (has_type ty (imax x y)))
(gen_int_select ty (IntSelectOP.Imax) (ext_int_if_need $true x ty) (ext_int_if_need $true y ty)))
(lower (has_type ty (smax x y)))
(gen_int_select ty (IntSelectOP.Smax) (ext_int_if_need $true x ty) (ext_int_if_need $true y ty)))
;;;;; Rules for `imin`;;;;;;;;;
;;;;; Rules for `smin`;;;;;;;;;
(rule
(lower (has_type ty (imin x y)))
(gen_int_select ty (IntSelectOP.Imin) (ext_int_if_need $true x ty) (ext_int_if_need $true y ty)))
(lower (has_type ty (smin x y)))
(gen_int_select ty (IntSelectOP.Smin) (ext_int_if_need $true x ty) (ext_int_if_need $true y ty)))
;;;;; Rules for `umax`;;;;;;;;;
(rule
(lower (has_type ty (umax x y)))

4
cranelift/codegen/src/isa/s390x/inst.isle
View File

@@ -4132,7 +4132,7 @@
(rule (vec_umax ty x y) (vec_rrr ty (vecop_umax ty) x y))
;; Helpers for generating `imax` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Helpers for generating `smax` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(decl vecop_smax (Type) VecBinaryOp)
(rule (vecop_smax $I8X16) (VecBinaryOp.SMax8x16))
@@ -4156,7 +4156,7 @@
(rule (vec_umin ty x y) (vec_rrr ty (vecop_umin ty) x y))
;; Helpers for generating `imin` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Helpers for generating `smin` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(decl vecop_smin (Type) VecBinaryOp)
(rule (vecop_smin $I8X16) (VecBinaryOp.SMin8x16))

8
cranelift/codegen/src/isa/s390x/lower.isle
View File

@@ -291,17 +291,17 @@
(vec_umin ty x y))
;;;; Rules for `imax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;; Rules for `smax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Signed maximum of two vector registers.
(rule (lower (has_type (ty_vec128 ty) (imax x y)))
(rule (lower (has_type (ty_vec128 ty) (smax x y)))
(vec_smax ty x y))
;;;; Rules for `imin` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;; Rules for `smin` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Signed minimum of two vector registers.
(rule (lower (has_type (ty_vec128 ty) (imin x y)))
(rule (lower (has_type (ty_vec128 ty) (smin x y)))
(vec_smin ty x y))

4
cranelift/codegen/src/isa/s390x/lower.rs
View File

@@ -58,9 +58,9 @@ impl LowerBackend for S390xBackend {
| Opcode::UsubSat
| Opcode::SsubSat
| Opcode::IaddPairwise
| Opcode::Imin
| Opcode::Smin
| Opcode::Umin
| Opcode::Imax
| Opcode::Smax
| Opcode::Umax
| Opcode::AvgRound
| Opcode::Iabs

22
cranelift/codegen/src/isa/x64/lower.isle
View File

@@ -1328,7 +1328,7 @@
(rule (vec_insert_lane $F64X2 vec val 1)
(x64_movlhps vec (reg_mem_to_xmm_mem val)))
;;;; Rules for `imin`, `imax`, `umin`, `umax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;; Rules for `smin`, `smax`, `umin`, `umax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; `i64` and smaller.
@@ -1350,32 +1350,32 @@
(rule -1 (lower (has_type (fits_in_64 ty) (umax x y)))
(cmp_and_choose ty (CC.NB) x y))
(rule -1 (lower (has_type (fits_in_64 ty) (imin x y)))
(rule -1 (lower (has_type (fits_in_64 ty) (smin x y)))
(cmp_and_choose ty (CC.L) x y))
(rule -1 (lower (has_type (fits_in_64 ty) (imax x y)))
(rule -1 (lower (has_type (fits_in_64 ty) (smax x y)))
(cmp_and_choose ty (CC.NL) x y))
;; SSE `imax`.
;; SSE `smax`.
(rule (lower (has_type $I8X16 (imax x y)))
(rule (lower (has_type $I8X16 (smax x y)))
(x64_pmaxsb x y))
(rule (lower (has_type $I16X8 (imax x y)))
(rule (lower (has_type $I16X8 (smax x y)))
(x64_pmaxsw x y))
(rule (lower (has_type $I32X4 (imax x y)))
(rule (lower (has_type $I32X4 (smax x y)))
(x64_pmaxsd x y))
;; SSE `imin`.
;; SSE `smin`.
(rule (lower (has_type $I8X16 (imin x y)))
(rule (lower (has_type $I8X16 (smin x y)))
(x64_pminsb x y))
(rule (lower (has_type $I16X8 (imin x y)))
(rule (lower (has_type $I16X8 (smin x y)))
(x64_pminsw x y))
(rule (lower (has_type $I32X4 (imin x y)))
(rule (lower (has_type $I32X4 (smin x y)))
(x64_pminsd x y))
;; SSE `umax`.

4
cranelift/codegen/src/isa/x64/lower.rs
View File

@@ -344,9 +344,9 @@ fn lower_insn_to_regs(
| Opcode::Imul
| Opcode::BandNot
| Opcode::Iabs
| Opcode::Imax
| Opcode::Smax
| Opcode::Umax
| Opcode::Imin
| Opcode::Smin
| Opcode::Umin
| Opcode::Bnot
| Opcode::Bitselect