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Support big- and little-endian lane order with bitcast (#5196)

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Add a MemFlags operand to the bitcast instruction, where only the
`big` and `little` flags are accepted.  These define the lane order
to be used when casting between types of different lane counts.

Update all users to pass an appropriate MemFlags argument.

Implement lane swaps where necessary in the s390x back-end.

This is the final part necessary to fix
https://github.com/bytecodealliance/wasmtime/issues/4566.
This commit is contained in:
Ulrich Weigand
2022-11-07 23:41:10 +01:00
committed by GitHub
parent 5cef53537b
commit 3e5938e65a
16 changed files with 295 additions and 51 deletions
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12
cranelift/codegen/src/isa/x64/lower.isle
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@@ -3298,25 +3298,25 @@
;; Rules for `bitcast` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type $I32 (bitcast src @ (value_type $F32))))
(rule (lower (has_type $I32 (bitcast _ src @ (value_type $F32))))
(bitcast_xmm_to_gpr $F32 src))
(rule (lower (has_type $F32 (bitcast src @ (value_type $I32))))
(rule (lower (has_type $F32 (bitcast _ src @ (value_type $I32))))
(bitcast_gpr_to_xmm $I32 src))
(rule (lower (has_type $I64 (bitcast src @ (value_type $F64))))
(rule (lower (has_type $I64 (bitcast _ src @ (value_type $F64))))
(bitcast_xmm_to_gpr $F64 src))
(rule (lower (has_type $F64 (bitcast src @ (value_type $I64))))
(rule (lower (has_type $F64 (bitcast _ src @ (value_type $I64))))
(bitcast_gpr_to_xmm $I64 src))
;; Bitcast between types residing in GPR registers is a no-op.
(rule 1 (lower (has_type (is_gpr_type _)
(bitcast x @ (value_type (is_gpr_type _))))) x)
(bitcast _ x @ (value_type (is_gpr_type _))))) x)
;; Bitcast between types residing in XMM registers is a no-op.
(rule 2 (lower (has_type (is_xmm_type _)
(bitcast x @ (value_type (is_xmm_type _))))) x)
(bitcast _ x @ (value_type (is_xmm_type _))))) x)
;; Rules for `fcopysign` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;