From 3d9f3bf7282306e7d5b58680c1463531994095e5 Mon Sep 17 00:00:00 2001
From: Andrew Brown <andrew.brown@intel.com>
Date: Wed, 30 Sep 2020 12:19:57 -0700
Subject: [PATCH] [machinst x64]: port CLIF tests related to comparison and
 lane operations

---
 .../isa/x64/simd-comparison-legalize.clif     |  39 ++++
 .../isa/x64/simd-comparison-run.clif          | 207 ++++++++++++++++++
 .../isa/x64/simd-lane-access-compile.clif     |  43 ++++
 .../isa/x64/simd-lane-access-run.clif         |  36 +++
 4 files changed, 325 insertions(+)
 create mode 100644 cranelift/filetests/filetests/isa/x64/simd-comparison-legalize.clif
 create mode 100644 cranelift/filetests/filetests/isa/x64/simd-comparison-run.clif

diff --git a/cranelift/filetests/filetests/isa/x64/simd-comparison-legalize.clif b/cranelift/filetests/filetests/isa/x64/simd-comparison-legalize.clif
new file mode 100644
index 0000000000..98dcf9a1a2
--- /dev/null
+++ b/cranelift/filetests/filetests/isa/x64/simd-comparison-legalize.clif
@@ -0,0 +1,39 @@
+test compile
+set enable_simd
+target x86_64 skylake
+feature "experimental_x64"
+
+function %icmp_ne_32x4(i32x4, i32x4) -> b32x4 {
+block0(v0: i32x4, v1: i32x4):
+    v2 = icmp ne v0, v1
+    return v2
+}
+; check:  pcmpeqd %xmm1, %xmm0
+; nextln: pcmpeqd %xmm1, %xmm1
+; nextln: pxor    %xmm1, %xmm0
+
+function %icmp_ugt_i32x4(i32x4, i32x4) -> b32x4 {
+block0(v0: i32x4, v1: i32x4):
+    v2 = icmp ugt v0, v1
+    return v2
+}
+; check:  pmaxud  %xmm1, %xmm0
+; nextln: pcmpeqd %xmm1, %xmm0
+; nextln: pcmpeqd %xmm1, %xmm1
+; nextln: pxor    %xmm1, %xmm0
+
+function %icmp_sge_i16x8(i16x8, i16x8) -> b16x8 {
+block0(v0: i16x8, v1: i16x8):
+    v2 = icmp sge v0, v1
+    return v2
+}
+; check:  pminsw  %xmm1, %xmm0
+; nextln: pcmpeqw %xmm1, %xmm0
+
+function %icmp_uge_i8x16(i8x16, i8x16) -> b8x16 {
+block0(v0: i8x16, v1: i8x16):
+    v2 = icmp uge v0, v1
+    return v2
+}
+; check:  pminub  %xmm1, %xmm0
+; nextln: pcmpeqb %xmm1, %xmm0
diff --git a/cranelift/filetests/filetests/isa/x64/simd-comparison-run.clif b/cranelift/filetests/filetests/isa/x64/simd-comparison-run.clif
new file mode 100644
index 0000000000..c22c56201a
--- /dev/null
+++ b/cranelift/filetests/filetests/isa/x64/simd-comparison-run.clif
@@ -0,0 +1,207 @@
+test run
+set enable_simd
+target x86_64
+feature "experimental_x64"
+
+function %icmp_eq_i8x16() -> b8 {
+block0:
+    v0 = vconst.i8x16 0x00
+    v1 = vconst.i8x16 0x00
+    v2 = icmp eq v0, v1
+    v3 = extractlane v2, 0
+    return v3
+}
+; run
+
+function %icmp_eq_i64x2() -> b64 {
+block0:
+    v0 = vconst.i64x2 0xffffffffffffffffffffffffffffffff
+    v1 = vconst.i64x2 0xffffffffffffffffffffffffffffffff
+    v2 = icmp eq v0, v1
+    v3 = extractlane v2, 1
+    return v3
+}
+; run
+
+function %icmp_ne_i32x4() -> b1 {
+block0:
+    v0 = vconst.i32x4 [0 1 2 3]
+    v1 = vconst.i32x4 [7 7 7 7]
+    v2 = icmp ne v0, v1
+    v3 = vall_true v2
+    return v3
+}
+; run
+
+function %icmp_ne_i16x8() -> b1 {
+block0:
+    v0 = vconst.i16x8 [0 1 2 3 4 5 6 7]
+    v1 = vconst.i16x8 [0 1 2 3 4 5 6 7]
+    v2 = icmp ne v0, v1
+    v3 = vall_true v2
+    v4 = bint.i32 v3
+    v5 = icmp_imm eq v4, 0
+    return v5
+}
+; run
+
+function %icmp_sgt_i8x16() -> b1 {
+block0:
+    v0 = vconst.i8x16 [0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0]
+    v1 = vconst.i8x16 [1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0xff]
+    v2 = icmp sgt v0, v1
+    v3 = raw_bitcast.i8x16 v2
+    v4 = vconst.i8x16 [0 0 0xff 0 0 0 0 0 0 0 0 0 0 0 0 0xff]
+    v7 = icmp eq v3, v4
+    v8 = vall_true v7
+    return v8
+}
+; run
+
+function %icmp_sgt_i64x2() -> b1 {
+block0:
+    v0 = vconst.i64x2 [0 -42]
+    v1 = vconst.i64x2 [-1 -43]
+    v2 = icmp sgt v0, v1
+    v8 = vall_true v2
+    return v8
+}
+; run
+
+function %icmp_ugt_i8x16() -> b1 {
+block0:
+    v0 = vconst.i8x16 [1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16]
+    v1 = vconst.i8x16 [0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1]
+    v2 = icmp ugt v0, v1
+    v8 = vall_true v2
+    return v8
+}
+; run
+
+function %icmp_sge_i16x8() -> b1 {
+block0:
+    v0 = vconst.i16x8 [-1 1 2 3 4 5 6 7]
+    v1 = vconst.i16x8 [-1 1 1 1 1 1 1 1]
+    v2 = icmp sge v0, v1
+    v8 = vall_true v2
+    return v8
+}
+; run
+
+function %icmp_uge_i32x4() -> b1 {
+block0:
+    v0 = vconst.i32x4 [1 2 3 4]
+    v1 = vconst.i32x4 [1 1 1 1]
+    v2 = icmp uge v0, v1
+    v8 = vall_true v2
+    return v8
+}
+; run
+
+function %icmp_slt_i32x4() -> b1 {
+block0:
+    v0 = vconst.i32x4 [-1 1 1 1]
+    v1 = vconst.i32x4 [1 2 3 4]
+    v2 = icmp slt v0, v1
+    v8 = vall_true v2
+    return v8
+}
+; run
+
+function %icmp_ult_i32x4() -> b1 {
+block0:
+    v0 = vconst.i32x4 [1 1 1 1]
+    v1 = vconst.i32x4 [-1 2 3 4] ; -1 = 0xffff... will be greater than 1 when unsigned
+    v2 = icmp ult v0, v1
+    v8 = vall_true v2
+    return v8
+}
+; run
+
+
+function %icmp_ult_i16x8() -> b1 {
+block0:
+    v0 = vconst.i16x8 [-1 -1 -1 -1 -1 -1 -1 -1]
+    v1 = vconst.i16x8 [-1 -1 -1 -1 -1 -1 -1 -1]
+    v2 = icmp ult v0, v1
+    v3 = vconst.i16x8 0x00
+    v4 = raw_bitcast.i16x8 v2
+    v5 = icmp eq v3, v4
+    v8 = vall_true v5
+    return v8
+}
+; run
+
+function %icmp_sle_i16x8() -> b1 {
+block0:
+    v0 = vconst.i16x8 [-1 -1 0 0 0 0 0 0]
+    v1 = vconst.i16x8 [-1  0 0 0 0 0 0 0]
+    v2 = icmp sle v0, v1
+    v8 = vall_true v2
+    return v8
+}
+; run
+
+function %icmp_ule_i16x8() -> b1 {
+block0:
+    v0 = vconst.i16x8 [-1  0 0 0 0 0 0 0]
+    v1 = vconst.i16x8 [-1 -1 0 0 0 0 0 0]
+    v2 = icmp ule v0, v1
+    v8 = vall_true v2
+    return v8
+}
+; run
+
+function %fcmp_eq_f32x4() -> b1 {
+block0:
+    v0 = vconst.f32x4 [0.0 -0x4.2 0x0.33333 -0.0]
+    v1 = vconst.f32x4 [0.0 -0x4.2 0x0.33333 -0.0]
+    v2 = fcmp eq v0, v1
+    v8 = vall_true v2
+    return v8
+}
+; run
+
+function %fcmp_lt_f32x4() -> b1 {
+block0:
+    v0 = vconst.f32x4 [0.0      -0x4.2  0x0.0       -0.0]
+    v1 = vconst.f32x4 [0x0.001  0x4.2   0x0.33333   0x1.0]
+    v2 = fcmp lt v0, v1
+    v8 = vall_true v2
+    return v8
+}
+; run
+
+function %fcmp_ge_f64x2() -> b1 {
+block0:
+    v0 = vconst.f64x2 [0x0.0  0x4.2]
+    v1 = vconst.f64x2 [0.0    0x4.1]
+    v2 = fcmp ge v0, v1
+    v8 = vall_true v2
+    return v8
+}
+; run
+
+function %fcmp_uno_f64x2() -> b1 {
+block0:
+    v0 = vconst.f64x2 [0.0  NaN]
+    v1 = vconst.f64x2 [NaN  0x4.1]
+    v2 = fcmp uno v0, v1
+    v8 = vall_true v2
+    return v8
+}
+; run
+
+function %fcmp_gt_nans_f32x4() -> b1 {
+block0:
+    v0 = vconst.f32x4 [NaN 0x42.0 -NaN NaN]
+    v1 = vconst.f32x4 [NaN NaN 0x42.0 Inf]
+    v2 = fcmp gt v0, v1
+    ; now check that the result v2 is all zeroes
+    v3 = vconst.i32x4 0x00
+    v4 = raw_bitcast.i32x4 v2
+    v5 = icmp eq v3, v4
+    v8 = vall_true v5
+    return v8
+}
+; run
diff --git a/cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif b/cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif
index eda6221813..17c04df772 100644
--- a/cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif
+++ b/cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif
@@ -48,3 +48,46 @@ block0:
 ; nextln: paddusb %xmm2, %xmm0
 ; nextln: pshufb  %xmm0, %xmm1
 ; nextln: movdqa  %xmm1, %xmm0
+
+
+
+;; splat
+
+function %splat_i8(i8) -> i8x16 {
+block0(v0: i8):
+    v1 = splat.i8x16 v0
+    return v1
+}
+; check:  fake_def %xmm0
+; nextln: pinsrb  $$0, %rdi, %xmm0
+; nextln: pxor    %xmm1, %xmm1
+; nextln: pshufb  %xmm1, %xmm0
+
+function %splat_b16() -> b16x8 {
+block0:
+    v0 = bconst.b16 true
+    v1 = splat.b16x8 v0
+    return v1
+}
+; check:  fake_def %xmm0
+; nextln: pinsrw  $$0, %r12, %xmm0
+; nextln: pinsrw  $$1, %r12, %xmm0
+; nextln: pshufd  $$0, %xmm0, %xmm0
+
+function %splat_i32(i32) -> i32x4 {
+block0(v0: i32):
+    v1 = splat.i32x4 v0
+    return v1
+}
+; check:  fake_def %xmm0
+; nextln: pinsrd  $$0, %rdi, %xmm0
+; nextln: pshufd  $$0, %xmm0, %xmm0
+
+function %splat_f64(f64) -> f64x2 {
+block0(v0: f64):
+    v1 = splat.f64x2 v0
+    return v1
+}
+; check:  fake_def %xmm1
+; nextln: movsd   %xmm0, %xmm1
+; nextln: movlhps %xmm0, %xmm1
diff --git a/cranelift/filetests/filetests/isa/x64/simd-lane-access-run.clif b/cranelift/filetests/filetests/isa/x64/simd-lane-access-run.clif
index d7b1ae2986..2ed0aed5d9 100644
--- a/cranelift/filetests/filetests/isa/x64/simd-lane-access-run.clif
+++ b/cranelift/filetests/filetests/isa/x64/simd-lane-access-run.clif
@@ -155,3 +155,39 @@ block0:
     return v8
 }
 ; run
+
+
+
+;; splat
+
+function %splat_i64x2() -> b1 {
+block0:
+    v0 = iconst.i64 -1
+    v1 = splat.i64x2 v0
+    v2 = vconst.i64x2 [-1 -1]
+    v3 = icmp eq v1, v2
+    v8 = vall_true v3
+    return v8
+}
+; run
+
+function %splat_i8(i8) -> i8x16 {
+block0(v0: i8):
+    v1 = splat.i8x16 v0
+    return v1
+}
+; run: %splat_i8(0xff) == [0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff]
+
+function %splat_i32(i32) -> i32x4 {
+block0(v0: i32):
+    v1 = splat.i32x4 v0
+    return v1
+}
+; run: %splat_i32(42) == [42 42 42 42]
+
+function %splat_f64(f64) -> f64x2 {
+block0(v0: f64):
+    v1 = splat.f64x2 v0
+    return v1
+}
+; run: %splat_f64(-0x1.1) == [-0x1.1 -0x1.1]