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Merge pull request #2975 from afonso360/aarch64-icmp

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aarch64: Implement lowering i128 icmp instructions
This commit is contained in:
Chris Fallin
2021-06-09 15:38:41 -07:00
committed by GitHub
parent caa85c2fa5 2643d2654c
commit 3d56728b86
7 changed files with 574 additions and 70 deletions
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4
cranelift/codegen/src/isa/aarch64/inst/emit.rs
View File

@@ -599,10 +599,14 @@ impl MachInstEmit for Inst {
ALUOp::Add64 => 0b10001011_000,
ALUOp::Adc32 => 0b00011010_000,
ALUOp::Adc64 => 0b10011010_000,
ALUOp::AdcS32 => 0b00111010_000,
ALUOp::AdcS64 => 0b10111010_000,
ALUOp::Sub32 => 0b01001011_000,
ALUOp::Sub64 => 0b11001011_000,
ALUOp::Sbc32 => 0b01011010_000,
ALUOp::Sbc64 => 0b11011010_000,
ALUOp::SbcS32 => 0b01111010_000,
ALUOp::SbcS64 => 0b11111010_000,
ALUOp::Orr32 => 0b00101010_000,
ALUOp::Orr64 => 0b10101010_000,
ALUOp::And32 => 0b00001010_000,

40
cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
View File

@@ -70,6 +70,26 @@ fn test_aarch64_binemit() {
"A400069A",
"adc x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AdcS32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
},
"4100033A",
"adcs w1, w2, w3",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AdcS64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A40006BA",
"adcs x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Sub32,
@@ -110,6 +130,26 @@ fn test_aarch64_binemit() {
"A40006DA",
"sbc x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::SbcS32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
},
"4100037A",
"sbcs w1, w2, w3",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::SbcS64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A40006FA",
"sbcs x4, x5, x6",
));
insns.push((
Inst::AluRRR {

10
cranelift/codegen/src/isa/aarch64/inst/mod.rs
View File

@@ -89,9 +89,15 @@ pub enum ALUOp {
/// Add with carry
Adc32,
Adc64,
/// Add with carry, settings flags
AdcS32,
AdcS64,
/// Subtract with carry
Sbc32,
Sbc64,
/// Subtract with carry, settings flags
SbcS32,
SbcS64,
}
/// An ALU operation with three arguments.
@@ -3216,8 +3222,12 @@ impl Inst {
ALUOp::Lsl64 => ("lsl", OperandSize::Size64),
ALUOp::Adc32 => ("adc", OperandSize::Size32),
ALUOp::Adc64 => ("adc", OperandSize::Size64),
ALUOp::AdcS32 => ("adcs", OperandSize::Size32),
ALUOp::AdcS64 => ("adcs", OperandSize::Size64),
ALUOp::Sbc32 => ("sbc", OperandSize::Size32),
ALUOp::Sbc64 => ("sbc", OperandSize::Size64),
ALUOp::SbcS32 => ("sbcs", OperandSize::Size32),
ALUOp::SbcS64 => ("sbcs", OperandSize::Size64),
}
}