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x64: Lower fcvt_to_{u,s}int{,_sat} in ISLE (#4704)

Browse Source 
https://github.com/bytecodealliance/wasmtime/pull/4704
This commit is contained in:
Trevor Elliott
2022-08-16 09:03:50 -07:00
committed by GitHub
parent 2ce03cce08
commit 3c1490dd59
6 changed files with 446 additions and 281 deletions
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272
cranelift/filetests/filetests/isa/x64/fcvt.clif
View File

@@ -200,3 +200,275 @@ block0(v0: i32x4):
; popq %rbp
; ret
function %f13(f32) -> i32 {
block0(v0: f32):
v1 = fcvt_to_uint.i32 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; cvt_float32_to_uint32_seq %xmm0, %eax, %r10, %xmm6
; movq %rbp, %rsp
; popq %rbp
; ret
function %f14(f32) -> i64 {
block0(v0: f32):
v1 = fcvt_to_uint.i64 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; cvt_float32_to_uint64_seq %xmm0, %rax, %r10, %xmm6
; movq %rbp, %rsp
; popq %rbp
; ret
function %f15(f64) -> i32 {
block0(v0: f64):
v1 = fcvt_to_uint.i32 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; cvt_float64_to_uint32_seq %xmm0, %eax, %r10, %xmm6
; movq %rbp, %rsp
; popq %rbp
; ret
function %f16(f64) -> i64 {
block0(v0: f64):
v1 = fcvt_to_uint.i64 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; cvt_float64_to_uint64_seq %xmm0, %rax, %r10, %xmm6
; movq %rbp, %rsp
; popq %rbp
; ret
function %f17(f32) -> i32 {
block0(v0: f32):
v1 = fcvt_to_uint_sat.i32 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; cvt_float32_to_uint32_sat_seq %xmm0, %eax, %r10, %xmm6
; movq %rbp, %rsp
; popq %rbp
; ret
function %f18(f32) -> i64 {
block0(v0: f32):
v1 = fcvt_to_uint_sat.i64 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; cvt_float32_to_uint64_sat_seq %xmm0, %rax, %r10, %xmm6
; movq %rbp, %rsp
; popq %rbp
; ret
function %f19(f64) -> i32 {
block0(v0: f64):
v1 = fcvt_to_uint_sat.i32 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; cvt_float64_to_uint32_sat_seq %xmm0, %eax, %r10, %xmm6
; movq %rbp, %rsp
; popq %rbp
; ret
function %f20(f64) -> i64 {
block0(v0: f64):
v1 = fcvt_to_uint_sat.i64 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; cvt_float64_to_uint64_sat_seq %xmm0, %rax, %r10, %xmm6
; movq %rbp, %rsp
; popq %rbp
; ret
function %f21(f32) -> i32 {
block0(v0: f32):
v1 = fcvt_to_sint.i32 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; cvt_float32_to_sint32_seq %xmm0, %eax, %r10, %xmm6
; movq %rbp, %rsp
; popq %rbp
; ret
function %f22(f32) -> i64 {
block0(v0: f32):
v1 = fcvt_to_sint.i64 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; cvt_float32_to_sint64_seq %xmm0, %rax, %r10, %xmm6
; movq %rbp, %rsp
; popq %rbp
; ret
function %f23(f64) -> i32 {
block0(v0: f64):
v1 = fcvt_to_sint.i32 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; cvt_float64_to_sint32_seq %xmm0, %eax, %r10, %xmm6
; movq %rbp, %rsp
; popq %rbp
; ret
function %f24(f64) -> i64 {
block0(v0: f64):
v1 = fcvt_to_sint.i64 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; cvt_float64_to_sint64_seq %xmm0, %rax, %r10, %xmm6
; movq %rbp, %rsp
; popq %rbp
; ret
function %f25(f32) -> i32 {
block0(v0: f32):
v1 = fcvt_to_sint_sat.i32 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; cvt_float32_to_sint32_sat_seq %xmm0, %eax, %r10, %xmm6
; movq %rbp, %rsp
; popq %rbp
; ret
function %f26(f32) -> i64 {
block0(v0: f32):
v1 = fcvt_to_sint_sat.i64 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; cvt_float32_to_sint64_sat_seq %xmm0, %rax, %r10, %xmm6
; movq %rbp, %rsp
; popq %rbp
; ret
function %f27(f64) -> i32 {
block0(v0: f64):
v1 = fcvt_to_sint_sat.i32 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; cvt_float64_to_sint32_sat_seq %xmm0, %eax, %r10, %xmm6
; movq %rbp, %rsp
; popq %rbp
; ret
function %f28(f64) -> i64 {
block0(v0: f64):
v1 = fcvt_to_sint_sat.i64 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; cvt_float64_to_sint64_sat_seq %xmm0, %rax, %r10, %xmm6
; movq %rbp, %rsp
; popq %rbp
; ret
function %f29(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = fcvt_to_uint_sat.i32x4 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; pxor %xmm3, %xmm3, %xmm3
; maxps %xmm0, %xmm3, %xmm0
; pcmpeqd %xmm8, %xmm8, %xmm8
; psrld %xmm8, $1, %xmm8
; cvtdq2ps %xmm8, %xmm14
; cvttps2dq %xmm0, %xmm13
; subps %xmm0, %xmm14, %xmm0
; cmpps $2, %xmm14, %xmm0, %xmm14
; cvttps2dq %xmm0, %xmm0
; pxor %xmm0, %xmm14, %xmm0
; pxor %xmm7, %xmm7, %xmm7
; pmaxsd %xmm0, %xmm7, %xmm0
; paddd %xmm0, %xmm13, %xmm0
; movq %rbp, %rsp
; popq %rbp
; ret
function %f30(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = fcvt_to_sint_sat.i32x4 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; movdqa %xmm0, %xmm5
; cmpps $0, %xmm5, %xmm0, %xmm5
; andps %xmm0, %xmm5, %xmm0
; pxor %xmm5, %xmm0, %xmm5
; cvttps2dq %xmm0, %xmm9
; movdqa %xmm9, %xmm0
; pand %xmm0, %xmm5, %xmm0
; psrad %xmm0, $31, %xmm0
; pxor %xmm0, %xmm9, %xmm0
; movq %rbp, %rsp
; popq %rbp
; ret

2
cranelift/filetests/filetests/runtests/simd-conversion.clif
View File

@@ -28,6 +28,7 @@ block0(v0:f32x4):
}
; run: %fcvt_to_sint_sat([0x0.0 -0x1.0 0x1.0 0x1.0p100]) == [0 -1 1 0x7FFFFFFF]
; run: %fcvt_to_sint_sat([-0x8.1 0x0.0 0x0.0 -0x1.0p100]) == [-8 0 0 0x80000000]
; run: %fcvt_to_sint_sat([+NaN +NaN +NaN +NaN]) == [0 0 0 0]
function %fcvt_to_uint_sat(f32x4) -> i32x4 {
block0(v0:f32x4):
@@ -37,3 +38,4 @@ block0(v0:f32x4):
; run: %fcvt_to_uint_sat([0x1.0 0x4.2 0x4.6 0x1.0p100]) == [1 4 4 0xFFFFFFFF]
; run: %fcvt_to_uint_sat([-0x8.1 -0x0.0 0x0.0 -0x1.0p100]) == [0 0 0 0]
; run: %fcvt_to_uint_sat([0xB2D05E00.0 0.0 0.0 0.0]) == [3000000000 0 0 0]
; run: %fcvt_to_uint_sat([+NaN +NaN +NaN +NaN]) == [0 0 0 0]