Enable simd_X_extadd_pairwise_X for AArch64

Lower to [u|s]addlp for AArch64.

Copyright (c) 2021, Arm Limited.

cranelift/filetests/filetests/isa/aarch64/simd-pairwise-add.clif

@@ -0,0 +1,124 @@
+test compile
+set unwind_info=false
+target aarch64
+
+
+function %fn1(i8x16) -> i16x8 {
+block0(v0: i8x16):
+  v1 = swiden_low v0
+  v2 = swiden_high v0
+  v3 = iadd_pairwise v1, v2
+  return v3
+}
+
+; check: stp fp
+; nextln: mov fp, sp
+; nextln: saddlp v0.8h, v0.16b
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %fn2(i8x16) -> i16x8 {
+block0(v0: i8x16):
+  v1 = uwiden_low v0
+  v2 = uwiden_high v0
+  v3 = iadd_pairwise v1, v2
+  return v3
+}
+
+; check: stp fp
+; nextln: mov fp, sp
+; nextln: uaddlp v0.8h, v0.16b
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %fn3(i16x8) -> i32x4 {
+block0(v0: i16x8):
+  v1 = swiden_low v0
+  v2 = swiden_high v0
+  v3 = iadd_pairwise v1, v2
+  return v3
+}
+
+; check: stp fp
+; nextln: mov fp, sp
+; nextln: saddlp v0.4s, v0.8h
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %fn4(i16x8) -> i32x4 {
+block0(v0: i16x8):
+  v1 = uwiden_low v0
+  v2 = uwiden_high v0
+  v3 = iadd_pairwise v1, v2
+  return v3
+}
+
+; check: stp fp
+; nextln: mov fp, sp
+; nextln: uaddlp v0.4s, v0.8h
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %fn5(i8x16, i8x16) -> i16x8 {
+block0(v0: i8x16, v1: i8x16):
+  v2 = swiden_low v0
+  v3 = swiden_high v1
+  v4 = iadd_pairwise v2, v3
+  return v4
+}
+
+; check: stp fp
+; nextln: mov fp, sp
+; nextln: sxtl v0.8h, v0.8b
+; nextln: sxtl2 v1.8h, v1.16b
+; nextln: addp v0.8h, v0.8h, v1.8h
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %fn6(i8x16, i8x16) -> i16x8 {
+block0(v0: i8x16, v1: i8x16):
+  v2 = uwiden_low v0
+  v3 = uwiden_high v1
+  v4 = iadd_pairwise v2, v3
+  return v4
+}
+
+; check: stp fp
+; nextln: mov fp, sp
+; nextln: uxtl v0.8h, v0.8b
+; nextln: uxtl2 v1.8h, v1.16b
+; nextln: addp v0.8h, v0.8h, v1.8h
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %fn7(i8x16) -> i16x8 {
+block0(v0: i8x16):
+  v1 = uwiden_low v0
+  v2 = swiden_high v0
+  v3 = iadd_pairwise v1, v2
+  return v3
+}
+
+; check: stp fp
+; nextln: mov fp, sp
+; nextln: uxtl v1.8h, v0.8b
+; nextln: sxtl2 v0.8h, v0.16b
+; nextln: addp v0.8h, v1.8h, v0.8h
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %fn8(i8x16) -> i16x8 {
+block0(v0: i8x16):
+  v1 = swiden_low v0
+  v2 = uwiden_high v0
+  v3 = iadd_pairwise v1, v2
+  return v3
+}
+
+; check: stp fp
+; nextln: mov fp, sp
+; nextln: sxtl v1.8h, v0.8b
+; nextln: uxtl2 v0.8h, v0.16b
+; nextln: addp v0.8h, v1.8h, v0.8h
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret