Emit compressed instruction encodings for instructions where constraints allow
This commit is contained in:
committed by
Jakob Stoklund Olesen
parent
2d4c860187
commit
3b66c0be40
@@ -1,6 +1,7 @@
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; binary emission of 64-bit code.
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test binemit
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set is_64bit
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set is_compressed
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isa intel haswell
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; The binary encodings can be verified with the command:
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@@ -104,16 +104,32 @@ impl SubTest for TestBinEmit {
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// value locations. The current error reporting is just crashing...
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let mut func = func.into_owned();
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let is_compressed = isa.flags().is_compressed();
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// Give an encoding to any instruction that doesn't already have one.
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for ebb in func.layout.ebbs() {
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for inst in func.layout.ebb_insts(ebb) {
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if !func.encodings[inst].is_legal() {
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if let Ok(enc) = isa.encode(
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let mut legal_encodings = isa.legal_encodings(
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&func.dfg,
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&func.dfg[inst],
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func.dfg.ctrl_typevar(inst),
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)
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{
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);
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let enc = if is_compressed {
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// Get the smallest legal encoding
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legal_encodings
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.filter(|e| {
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let recipe_constraints = &encinfo.constraints[e.recipe()];
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recipe_constraints.satisfied(inst, &func)
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})
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.min_by_key(|&e| encinfo.bytes(e))
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} else {
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// If not using compressed, just use the first encoding.
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legal_encodings.next()
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};
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if let Some(enc) = enc {
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func.encodings[inst] = enc;
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}
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}
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@@ -13,7 +13,7 @@ from .registers import GPR, ABCD, FPR
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try:
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from typing import Tuple, Dict # noqa
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from cdsl.instructions import InstructionFormat # noqa
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from cdsl.isa import ConstraintSeq, BranchRange, PredNode # noqa
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from cdsl.isa import ConstraintSeq, BranchRange, PredNode, OperandConstraint # noqa
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except ImportError:
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pass
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@@ -9,6 +9,7 @@
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use binemit::CodeOffset;
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use isa::{RegClass, RegUnit};
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use ir::{Function, ValueLoc, Inst};
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/// Register constraint for a single value operand or instruction result.
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pub struct OperandConstraint {
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@@ -21,6 +22,34 @@ pub struct OperandConstraint {
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pub regclass: RegClass,
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}
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impl OperandConstraint {
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/// Check if this operand constraint is satisfied by the given value location.
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/// For tied constraints, this only checks the register class, not that the
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/// counterpart operand has the same value location.
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pub fn satisfied(&self, loc: ValueLoc) -> bool {
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match self.kind {
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ConstraintKind::Reg |
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ConstraintKind::Tied(_) => {
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if let ValueLoc::Reg(reg) = loc {
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self.regclass.contains(reg)
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} else {
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false
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}
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}
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ConstraintKind::FixedReg(reg) => {
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loc == ValueLoc::Reg(reg) && self.regclass.contains(reg)
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}
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ConstraintKind::Stack => {
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if let ValueLoc::Stack(_) = loc {
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true
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} else {
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false
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}
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}
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}
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}
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}
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/// The different kinds of operand constraints.
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#[derive(Clone, Copy, PartialEq, Eq)]
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pub enum ConstraintKind {
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@@ -78,6 +107,36 @@ pub struct RecipeConstraints {
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pub tied_ops: bool,
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}
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impl RecipeConstraints {
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/// Check that these constraints are satisfied by the operands on `inst`.
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pub fn satisfied(&self, inst: Inst, func: &Function) -> bool {
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for (&arg, constraint) in func.dfg.inst_args(inst).iter().zip(self.ins) {
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let loc = func.locations[arg];
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if let ConstraintKind::Tied(out_index) = constraint.kind {
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let out_val = func.dfg.inst_results(inst)[out_index as usize];
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let out_loc = func.locations[out_val];
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if loc != out_loc {
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return false;
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}
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}
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if !constraint.satisfied(loc) {
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return false;
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}
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}
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for (&arg, constraint) in func.dfg.inst_results(inst).iter().zip(self.outs) {
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let loc = func.locations[arg];
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if !constraint.satisfied(loc) {
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return false;
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}
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}
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true
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}
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}
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/// Constraints on the range of a branch instruction.
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///
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/// A branch instruction usually encodes its destination as a signed n-bit offset from an origin.
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