diff --git a/cranelift/filetests/isa/intel/binary32.cton b/cranelift/filetests/isa/intel/binary32.cton
index 81274ab91f..a4834baaab 100644
--- a/cranelift/filetests/isa/intel/binary32.cton
+++ b/cranelift/filetests/isa/intel/binary32.cton
@@ -140,6 +140,13 @@ ebb0:
     ; asm: movl %ecx, %esi
     [-,%rsi]             v81 = copy v1           ; bin: 89 ce
 
+    ; Copy Special
+    ; asm: movl %esp, %ebp
+    copy_special %rsp -> %rbp                   ; bin: 89 e5
+    ; asm: movl %ebp, %esp
+    copy_special %rbp -> %rsp                   ; bin: 89 ec
+
+
     ; Load/Store instructions.
 
     ; Register indirect addressing with no displacement.
diff --git a/cranelift/filetests/isa/intel/binary64.cton b/cranelift/filetests/isa/intel/binary64.cton
index f695d1b227..8d57b231e6 100644
--- a/cranelift/filetests/isa/intel/binary64.cton
+++ b/cranelift/filetests/isa/intel/binary64.cton
@@ -155,6 +155,17 @@ ebb0:
     ; asm: movq %rcx, %r10
     [-,%r10]             v112 = copy v1          ; bin: 49 89 ca
 
+    ; Copy Special
+    ; asm: movq %rsp, %rbp
+    copy_special %rsp -> %rbp                   ; bin: 48 89 e5
+    ; asm: movq %r10, %r11
+    copy_special %r10 -> %r11                   ; bin: 4d 89 d3
+    ; asm: movq %rsp, %r11
+    copy_special %rsp -> %r11                   ; bin: 49 89 e3
+    ; asm: movq %r10, %rsp
+    copy_special %r10 -> %rsp                   ; bin: 4c 89 d4
+
+
     ; Load/Store instructions.
 
     ; Register indirect addressing with no displacement.
diff --git a/cranelift/filetests/isa/intel/prologue-epilogue.cton b/cranelift/filetests/isa/intel/prologue-epilogue.cton
index 773a47da0c..10b6e9cf93 100644
--- a/cranelift/filetests/isa/intel/prologue-epilogue.cton
+++ b/cranelift/filetests/isa/intel/prologue-epilogue.cton
@@ -1,6 +1,6 @@
-test legalizer
 test binemit
-set is_64bit=1
+set is_64bit
+set is_compressed
 isa intel haswell
 
 function %foo(f64 [%xmm0], i64 fp [%rbp], i64 csr [%rbx], i64 csr [%r12]) -> i64 csr [%r12], i64 csr [%rbx], i64 fp [%rbp] {
diff --git a/cranelift/filetests/parser/tiny.cton b/cranelift/filetests/parser/tiny.cton
index 13513a2b6c..20c4bbe2b3 100644
--- a/cranelift/filetests/parser/tiny.cton
+++ b/cranelift/filetests/parser/tiny.cton
@@ -186,3 +186,17 @@ ebb0(v1: i32):
 ; nextln:     regfill $v1, $ss0 -> %10
 ; nextln:     return
 ; nextln: }
+
+; Register copies.
+function %copy_special() {
+ebb0:
+    copy_special %10 -> %20
+    copy_special %20 -> %10
+    return
+}
+; sameln: function %copy_special() native {
+; nextln: ebb0:
+; nextln:     copy_special %10 -> %20
+; nextln:     copy_special %20 -> %10
+; nextln:     return
+; nextln: }
diff --git a/lib/cretonne/meta/base/instructions.py b/lib/cretonne/meta/base/instructions.py
index 4eef992e99..bbfb9ddbe8 100644
--- a/lib/cretonne/meta/base/instructions.py
+++ b/lib/cretonne/meta/base/instructions.py
@@ -539,7 +539,12 @@ regmove = Instruction(
 
 copy_special = Instruction(
         'copy_special', r"""
-        Copies a value from one special register to another. e.g. rbp -> rsp.
+        Copies the contents of ''src'' register to ''dst'' register.
+
+        This instructions copies the contents of one register to another
+        register without involving any SSA values. This is used for copying
+        special registers, e.g. copying the stack register to the frame
+        register in a function prologue.
         """,
         ins=(src, dst),
         other_side_effects=True)
diff --git a/lib/cretonne/meta/isa/intel/encodings.py b/lib/cretonne/meta/isa/intel/encodings.py
index fd75fef2a2..42f125c93f 100644
--- a/lib/cretonne/meta/isa/intel/encodings.py
+++ b/lib/cretonne/meta/isa/intel/encodings.py
@@ -232,7 +232,7 @@ enc_i32_i64(x86.push, r.pushq, 0x50)
 enc_i32_i64(x86.pop, r.popq, 0x58)
 
 # Copy Special
-enc_i64(base.copy_special, r.copysp, 0x89, w=1)
+I64.enc(base.copy_special, *r.copysp.rex(0x89, w=1))
 I32.enc(base.copy_special, *r.copysp(0x89))
 
 # Adjust SP Imm