arm64: Implement SIMD shift instructions

Copyright (c) 2020, Arm Limited.

cranelift/codegen/src/isa/aarch64/inst/mod.rs

@@ -249,6 +249,10 @@ pub enum VecALUOp {
     Sub,
     /// Multiply
     Mul,
+    /// Signed shift left
+    Sshl,
+    /// Unsigned shift left
+    Ushl,
 }
 
 /// A Vector miscellaneous operation with two registers.
@@ -2751,6 +2755,8 @@ impl ShowWithRRU for Inst {
                     VecALUOp::Add => ("add", true, ty),
                     VecALUOp::Sub => ("sub", true, ty),
                     VecALUOp::Mul => ("mul", true, ty),
+                    VecALUOp::Sshl => ("sshl", true, ty),
+                    VecALUOp::Ushl => ("ushl", true, ty),
                 };
 
                 let show_vreg_fn: fn(Reg, Option<&RealRegUniverse>, Type) -> String = if vector {