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Add RISC-V encodings for brz and brnz.

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These branches compare a register to zero. RISC-V implements this with
the %x0 hard-coded zero register.
This commit is contained in:
Jakob Stoklund Olesen
2017-04-03 15:20:57 -07:00
parent 39e102b155
commit 3a47b40ff8
4 changed files with 32 additions and 2 deletions
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11
lib/cretonne/meta/isa/riscv/encodings.py
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@@ -6,7 +6,7 @@ from base import instructions as base
from base.immediates import intcc
from .defs import RV32, RV64
from .recipes import OPIMM, OPIMM32, OP, OP32, LUI, BRANCH
from .recipes import JALR, R, Rshamt, Ricmp, I, Iicmp, Iret, U, SB
from .recipes import JALR, R, Rshamt, Ricmp, I, Iicmp, Iret, U, SB, SBzero
from .settings import use_m
from cdsl.ast import Var
@@ -93,6 +93,15 @@ for cond, f3 in [
RV32.enc(base.br_icmp.i32(cond, x, y, dest, args), SB, BRANCH(f3))
RV64.enc(base.br_icmp.i64(cond, x, y, dest, args), SB, BRANCH(f3))
for inst, f3 in [
(base.brz, 0b000),
(base.brnz, 0b001)
]:
RV32.enc(inst.i32, SBzero, BRANCH(f3))
RV64.enc(inst.i64, SBzero, BRANCH(f3))
RV32.enc(inst.b1, SBzero, BRANCH(f3))
RV64.enc(inst.b1, SBzero, BRANCH(f3))
# Returns are a special case of JALR.
# Note: Return stack predictors will only recognize this as a return when the
# return address is provided in `x1`. We may want a special encoding to enforce