Add RISC-V encodings for brz and brnz.

These branches compare a register to zero. RISC-V implements this with the %x0 hard-coded zero register.
2017-04-03 15:20:57 -07:00
parent 39e102b155
commit 3a47b40ff8
4 changed files with 32 additions and 2 deletions
--- a/filetests/isa/riscv/binary32.cton
+++ b/filetests/isa/riscv/binary32.cton
@@ -91,5 +91,10 @@ ebb0:
    ; bgeu
    br_icmp uge, v1, v2, ebb0           ; bin: Branch(ebb0) 01557063

+    ; beq x, %x0
+    brz v1, ebb0                        ; bin: Branch(ebb0) 00050063
+    ; bne x, %x0
+    brnz v1, ebb0                       ; bin: Branch(ebb0) 00051063
+
    return
 }