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Add conditional branch encodings for RISC-V.

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Not all br_icmp opcodes are present in the ISA. The missing ones can be
reached by commuting operands.

Don't attempt to encode EBB offsets yet. For now just emit an EBB
relocation for the branch instruction.
This commit is contained in:
Jakob Stoklund Olesen
2017-04-03 15:07:08 -07:00
parent d2ddc700a8
commit 39e102b155
9 changed files with 124 additions and 12 deletions
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16
filetests/isa/riscv/binary32.cton
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@@ -75,5 +75,21 @@ ebb0:
[-,%x7] v140 = iconst.i32 0x12345000 ; bin: 123453b7
[-,%x16] v141 = iconst.i32 0xffffffff_fedcb000 ; bin: fedcb837
; Control Transfer Instructions
; beq
br_icmp eq, v1, v2, ebb0 ; bin: Branch(ebb0) 01550063
; bne
br_icmp ne, v1, v2, ebb0 ; bin: Branch(ebb0) 01551063
; blt
br_icmp slt, v1, v2, ebb0 ; bin: Branch(ebb0) 01554063
; bge
br_icmp sge, v1, v2, ebb0 ; bin: Branch(ebb0) 01555063
; bltu
br_icmp ult, v1, v2, ebb0 ; bin: Branch(ebb0) 01556063
; bgeu
br_icmp uge, v1, v2, ebb0 ; bin: Branch(ebb0) 01557063
return
}