From 39c0a28d770de2e1ea4ae476ff6b61c009abdd95 Mon Sep 17 00:00:00 2001 From: Andrew Brown Date: Fri, 20 Mar 2020 18:56:06 -0700 Subject: [PATCH] Zero-extend the result of `extractlane` Previously, `extractlane` results did not have the expected `uextend` because this work was completed by PEXTRB in x86. Since other architectures may eventually need this and since leaving the `uextend` out leaves the extracted values with the wrong type (`i16` instead of `i32`), the `uextend` is re-added. The duplicated zero-extension work (from PEXTRB and MOVZX) could be fixed by a later optimization. --- cranelift/wasm/src/code_translator.rs | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/cranelift/wasm/src/code_translator.rs b/cranelift/wasm/src/code_translator.rs index 5f38d85ea2..07f7f7aab6 100644 --- a/cranelift/wasm/src/code_translator.rs +++ b/cranelift/wasm/src/code_translator.rs @@ -1282,8 +1282,11 @@ pub fn translate_operator( } Operator::I8x16ExtractLaneU { lane } | Operator::I16x8ExtractLaneU { lane } => { let vector = pop1_with_bitcast(state, type_of(op), builder); - state.push1(builder.ins().extractlane(vector, lane.clone())); - // on x86, PEXTRB zeroes the upper bits of the destination register of extractlane so uextend is elided; of course, this depends on extractlane being legalized to a PEXTRB + let extracted = builder.ins().extractlane(vector, lane.clone()); + state.push1(builder.ins().uextend(I32, extracted)); + // On x86, PEXTRB zeroes the upper bits of the destination register of extractlane so + // uextend could be elided; for now, uextend is needed for Cranelift's type checks to + // work. } Operator::I32x4ExtractLane { lane } | Operator::I64x2ExtractLane { lane }