Remove LoadSplat opcode, in preparation for pattern-matching Load+Splat.
This was added as an incremental step to improve AArch64 code quality in PR #2278. At the time, we did not have a way to pattern-match the load + splat opcode sequence that the relevant Wasm opcodes lowered to. However, now with PR #2366, we can merge effectful instructions such as loads into other ops, and so we can do this pattern matching directly. The pattern-matching update will come in a subsequent commit.
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@@ -1414,17 +1414,16 @@ pub fn translate_operator<FE: FuncEnvironment + ?Sized>(
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| Operator::V128Load16Splat { memarg }
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| Operator::V128Load32Splat { memarg }
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| Operator::V128Load64Splat { memarg } => {
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let opcode = ir::Opcode::LoadSplat;
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let result_ty = type_of(op);
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let (flags, base, offset) = prepare_load(
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translate_load(
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memarg,
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mem_op_size(opcode, result_ty.lane_type()),
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ir::Opcode::Load,
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type_of(op).lane_type(),
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builder,
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state,
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environ,
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)?;
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let (load, dfg) = builder.ins().Load(opcode, result_ty, flags, offset, base);
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state.push1(dfg.first_result(load))
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let splatted = builder.ins().splat(type_of(op), state.pop1());
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state.push1(splatted)
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}
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Operator::V128Load32Zero { memarg } | Operator::V128Load64Zero { memarg } => {
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translate_load(
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@@ -2103,7 +2102,7 @@ fn mem_op_size(opcode: ir::Opcode, ty: Type) -> u32 {
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ir::Opcode::Istore8 | ir::Opcode::Sload8 | ir::Opcode::Uload8 => 1,
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ir::Opcode::Istore16 | ir::Opcode::Sload16 | ir::Opcode::Uload16 => 2,
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ir::Opcode::Istore32 | ir::Opcode::Sload32 | ir::Opcode::Uload32 => 4,
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ir::Opcode::Store | ir::Opcode::Load | ir::Opcode::LoadSplat => ty.bytes(),
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ir::Opcode::Store | ir::Opcode::Load => ty.bytes(),
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_ => panic!("unknown size of mem op for {:?}", opcode),
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}
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}
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