diff --git a/cranelift/filetests/isa/x86/binary64.cton b/cranelift/filetests/isa/x86/binary64.cton
index 96788c629b..b9e56c1ccb 100644
--- a/cranelift/filetests/isa/x86/binary64.cton
+++ b/cranelift/filetests/isa/x86/binary64.cton
@@ -913,6 +913,15 @@ ebb0:
     ; asm: movsbl -50000(%rsi), %edx
     [-,%rdx]            v39 = sload8.i32 v2-50000         ; bin: heap_oob 0f be 96 ffff3cb0
 
+    ; Integer Register Operations.
+
+    ; asm: notl %ecx
+    [-,%rcx]             v4000 = bnot v1       ; bin: f7 d1
+    ; asm: notl %esi
+    [-,%rsi]             v4001 = bnot v2       ; bin: f7 d6
+    ; asm: notl %r10d
+    [-,%r10]             v4002 = bnot v3       ; bin: 41 f7 d2
+
     ; Integer Register-Register Operations.
 
     ; asm: addl %esi, %ecx
diff --git a/lib/codegen/meta/isa/x86/encodings.py b/lib/codegen/meta/isa/x86/encodings.py
index 2909aac315..62dbf1dcf7 100644
--- a/lib/codegen/meta/isa/x86/encodings.py
+++ b/lib/codegen/meta/isa/x86/encodings.py
@@ -150,6 +150,9 @@ for inst,           opc in [
         (base.bxor, 0x31)]:
     enc_i32_i64(inst, r.rr, opc)
 
+# x86 has a bitwise not instruction NOT.
+enc_i32_i64(base.bnot, r.ur, 0xf7, rrr=2)
+
 # Also add a `b1` encodings for the logic instructions.
 # TODO: Should this be done with 8-bit instructions? It would improve
 # partial register dependencies.
diff --git a/lib/codegen/meta/isa/x86/recipes.py b/lib/codegen/meta/isa/x86/recipes.py
index 8828f8a06e..1caf6136d1 100644
--- a/lib/codegen/meta/isa/x86/recipes.py
+++ b/lib/codegen/meta/isa/x86/recipes.py
@@ -348,6 +348,14 @@ fax = TailRecipe(
         modrm_rr(in_reg0, in_reg1, sink);
         ''')
 
+# XX /n for a unary operation with extension bits.
+ur = TailRecipe(
+        'ur', Unary, size=1, ins=GPR, outs=0,
+        emit='''
+        PUT_OP(bits, rex1(in_reg0), sink);
+        modrm_r_bits(in_reg0, bits, sink);
+        ''')
+
 # XX /r, but for a unary operator with separate input/output register, like
 # copies. MR form, preserving flags.
 umr = TailRecipe(