From 38ef98700f19dcbc75422d5d596b34b78f3d0b63 Mon Sep 17 00:00:00 2001
From: Johnnie Birch <45402135+jlb6740@users.noreply.github.com>
Date: Mon, 10 Aug 2020 23:26:21 -0700
Subject: [PATCH] Adds packed integer subtraction

---
 cranelift/codegen/src/isa/x64/inst/args.rs    | 12 ++++++++++
 cranelift/codegen/src/isa/x64/inst/emit.rs    |  4 ++++
 .../codegen/src/isa/x64/inst/emit_tests.rs    | 24 +++++++++++++++++++
 cranelift/codegen/src/isa/x64/lower.rs        |  7 ++++++
 4 files changed, 47 insertions(+)

diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs
index 100aefe2d5..9885102b66 100644
--- a/cranelift/codegen/src/isa/x64/inst/args.rs
+++ b/cranelift/codegen/src/isa/x64/inst/args.rs
@@ -403,6 +403,10 @@ pub enum SseOpcode {
     Psrlw,
     Psrld,
     Psrlq,
+    Psubb,
+    Psubd,
+    Psubq,
+    Psubw,
     Rcpss,
     Roundss,
     Roundsd,
@@ -495,6 +499,10 @@ impl SseOpcode {
             | SseOpcode::Psrlw
             | SseOpcode::Psrld
             | SseOpcode::Psrlq
+            | SseOpcode::Psubb
+            | SseOpcode::Psubd
+            | SseOpcode::Psubq
+            | SseOpcode::Psubw
             | SseOpcode::Sqrtpd
             | SseOpcode::Sqrtsd
             | SseOpcode::Subpd
@@ -579,6 +587,10 @@ impl fmt::Debug for SseOpcode {
             SseOpcode::Psrlw => "psrlw",
             SseOpcode::Psrld => "psrld",
             SseOpcode::Psrlq => "psrlq",
+            SseOpcode::Psubb => "psubb",
+            SseOpcode::Psubd => "psubd",
+            SseOpcode::Psubq => "psubq",
+            SseOpcode::Psubw => "psubw",
             SseOpcode::Rcpss => "rcpss",
             SseOpcode::Roundss => "roundss",
             SseOpcode::Roundsd => "roundsd",
diff --git a/cranelift/codegen/src/isa/x64/inst/emit.rs b/cranelift/codegen/src/isa/x64/inst/emit.rs
index a2100ec29f..f0932b73c4 100644
--- a/cranelift/codegen/src/isa/x64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/x64/inst/emit.rs
@@ -1663,6 +1663,10 @@ pub(crate) fn emit(
                 SseOpcode::Paddd => (LegacyPrefix::_66, 0x0FFE),
                 SseOpcode::Paddq => (LegacyPrefix::_66, 0x0FD4),
                 SseOpcode::Paddw => (LegacyPrefix::_66, 0x0FFD),
+                SseOpcode::Psubb => (LegacyPrefix::_66, 0x0FF8),
+                SseOpcode::Psubd => (LegacyPrefix::_66, 0x0FFA),
+                SseOpcode::Psubq => (LegacyPrefix::_66, 0x0FFB),
+                SseOpcode::Psubw => (LegacyPrefix::_66, 0x0FF9),
                 SseOpcode::Subps => (LegacyPrefix::None, 0x0F5C),
                 SseOpcode::Subpd => (LegacyPrefix::_66, 0x0F5C),
                 SseOpcode::Subss => (LegacyPrefix::_F3, 0x0F5C),
diff --git a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs
index 719d2566d3..877c2282b4 100644
--- a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs
+++ b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs
@@ -3038,6 +3038,30 @@ fn test_x64_emit() {
         "paddq   %xmm1, %xmm8",
     ));
 
+    insns.push((
+        Inst::xmm_rm_r(SseOpcode::Psubb, RegMem::reg(xmm5), w_xmm9),
+        "66440FF8CD",
+        "psubb   %xmm5, %xmm9",
+    ));
+
+    insns.push((
+        Inst::xmm_rm_r(SseOpcode::Psubw, RegMem::reg(xmm6), w_xmm7),
+        "660FF9FE",
+        "psubw   %xmm6, %xmm7",
+    ));
+
+    insns.push((
+        Inst::xmm_rm_r(SseOpcode::Psubd, RegMem::reg(xmm13), w_xmm12),
+        "66450FFAE5",
+        "psubd   %xmm13, %xmm12",
+    ));
+
+    insns.push((
+        Inst::xmm_rm_r(SseOpcode::Psubq, RegMem::reg(xmm8), w_xmm1),
+        "66410FFBC8",
+        "psubq   %xmm8, %xmm1",
+    ));
+
     // XMM_Mov_R_M: float stores
     insns.push((
         Inst::xmm_mov_r_m(SseOpcode::Movss, xmm15, Amode::imm_reg(128, r12), None),
diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs
index 407a9a687e..66d16c894d 100644
--- a/cranelift/codegen/src/isa/x64/lower.rs
+++ b/cranelift/codegen/src/isa/x64/lower.rs
@@ -350,6 +350,13 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
                         types::I64X2 => SseOpcode::Paddq,
                         _ => panic!("Unsupported type for packed Iadd instruction"),
                     },
+                    Opcode::Isub => match ty {
+                        types::I8X16 => SseOpcode::Psubb,
+                        types::I16X8 => SseOpcode::Psubw,
+                        types::I32X4 => SseOpcode::Psubd,
+                        types::I64X2 => SseOpcode::Psubq,
+                        _ => panic!("Unsupported type for packed Isub instruction"),
+                    },
                     _ => panic!("Unsupported packed instruction"),
                 };
                 let lhs = input_to_reg(ctx, inputs[0]);