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fix issue 5714. (#5845)

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* fix issue 5714.

* add target for regression test.

* remove x86_64 test because of not implemented.
This commit is contained in:
yuyang
2023-02-27 00:25:38 +08:00
committed by GitHub
parent 66cb13cb4b
commit 3864286596
3 changed files with 31 additions and 6 deletions
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10
cranelift/codegen/src/isa/riscv64/inst/emit.rs
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@@ -1751,23 +1751,23 @@ impl MachInstEmit for Inst {
if out_type.bits() < 32 && is_signed { if out_type.bits() < 32 && is_signed {
// load value part mask. // load value part mask.
Inst::load_constant_u32( Inst::load_constant_u32(
tmp, writable_spilltmp_reg(),
if 16 == out_type.bits() { if 16 == out_type.bits() {
(u16::MAX >> 1) as u64 (u16::MAX >> 1) as u64
} else { } else {
// I8 // I8
(u8::MAX >> 1) as u64 (u8::MAX >> 1) as u64
}, },
&mut |_| writable_spilltmp_reg(), &mut |_| writable_spilltmp_reg2(),
) )
.into_iter() .into_iter()
.for_each(|x| x.emit(&[], sink, emit_info, state)); .for_each(|x| x.emit(&[], sink, emit_info, state));
// keep value part. // keep value part.
Inst::AluRRR { Inst::AluRRR {
alu_op: AluOPRRR::And, alu_op: AluOPRRR::And,
rd: tmp, rd: writable_spilltmp_reg(),
rs1: rd.to_reg(), rs1: rd.to_reg(),
rs2: tmp.to_reg(), rs2: spilltmp_reg(),
} }
.emit(&[], sink, emit_info, state); .emit(&[], sink, emit_info, state);
// extact sign bit. // extact sign bit.
@@ -1795,7 +1795,7 @@ impl MachInstEmit for Inst {
alu_op: AluOPRRR::Or, alu_op: AluOPRRR::Or,
rd: rd, rd: rd,
rs1: rd.to_reg(), rs1: rd.to_reg(),
rs2: tmp.to_reg(), rs2: spilltmp_reg(),
} }
.emit(&[], sink, emit_info, state); .emit(&[], sink, emit_info, state);
} }

2
cranelift/codegen/src/isa/riscv64/inst/mod.rs
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@@ -524,7 +524,7 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
&Inst::FcvtToInt { rd, rs, tmp, .. } => { &Inst::FcvtToInt { rd, rs, tmp, .. } => {
collector.reg_use(rs); collector.reg_use(rs);
collector.reg_early_def(tmp); collector.reg_early_def(tmp);
collector.reg_def(rd); collector.reg_early_def(rd);
} }
&Inst::SelectIf { &Inst::SelectIf {
ref rd, ref rd,

25
cranelift/filetests/filetests/runtests/issue5714.clif Normal file
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@@ -0,0 +1,25 @@
test interpret
test run
target aarch64
target s390x
target riscv64
function %a(i32 sext, f64, f32, i64 uext) -> f32, i8, i8 system_v {
block0(v0: i32, v1: f64, v2: f32, v3: i64):
v12 -> v1
v14 -> v2
v16 -> v2
v4 = iconst.i16 0x4242
v5 = iconst.i64 0x0042_4242_4242_4242
jump block1
block1:
v13 = fcvt_to_sint_sat.i8 v12
v15 -> v13
brif v13, block2, block1
block2:
return v14, v15, v15
}
; run: %a(1111441986, -0x1.ffa8b425b4242p128, 0x0.00859ep-126, 0) == [0x0.00859ep-126, -128, -128]