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fix issue 5714. (#5845)

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* fix issue 5714.

* add target for regression test.

* remove x86_64 test because of not implemented.
This commit is contained in:
yuyang
2023-02-27 00:25:38 +08:00
committed by GitHub
parent 66cb13cb4b
commit 3864286596
3 changed files with 31 additions and 6 deletions
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10
cranelift/codegen/src/isa/riscv64/inst/emit.rs
View File

@@ -1751,23 +1751,23 @@ impl MachInstEmit for Inst {
if out_type.bits() < 32 && is_signed {
// load value part mask.
Inst::load_constant_u32(
tmp,
writable_spilltmp_reg(),
if 16 == out_type.bits() {
(u16::MAX >> 1) as u64
} else {
// I8
(u8::MAX >> 1) as u64
},
&mut |_| writable_spilltmp_reg(),
&mut |_| writable_spilltmp_reg2(),
)
.into_iter()
.for_each(|x| x.emit(&[], sink, emit_info, state));
// keep value part.
Inst::AluRRR {
alu_op: AluOPRRR::And,
rd: tmp,
rd: writable_spilltmp_reg(),
rs1: rd.to_reg(),
rs2: tmp.to_reg(),
rs2: spilltmp_reg(),
}
.emit(&[], sink, emit_info, state);
// extact sign bit.
@@ -1795,7 +1795,7 @@ impl MachInstEmit for Inst {
alu_op: AluOPRRR::Or,
rd: rd,
rs1: rd.to_reg(),
rs2: tmp.to_reg(),
rs2: spilltmp_reg(),
}
.emit(&[], sink, emit_info, state);
}

2
cranelift/codegen/src/isa/riscv64/inst/mod.rs
View File

@@ -524,7 +524,7 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
&Inst::FcvtToInt { rd, rs, tmp, .. } => {
collector.reg_use(rs);
collector.reg_early_def(tmp);
collector.reg_def(rd);
collector.reg_early_def(rd);
}
&Inst::SelectIf {
ref rd,