machinst x64: revamp integer immediate emission;
In particular: - try to optimize the integer emission into a 32-bit emission, when the high bits are all zero, and stop relying on the caller of `imm_r` to ensure this. - rename `Inst::imm_r`/`Inst::Imm_R` to `Inst::imm`/`Inst::Imm`. - generate a sign-extending mov 32-bit immediate to 64-bits, whenever possible. - fix a few places where the previous commit did introduce the generation of zero-constants with xor, when calling `put_input_to_reg`, thus clobbering the flags before they were read.
This commit is contained in:
Benjamin Bouvier
@@ -107,7 +107,7 @@ pub enum Inst {
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/// Constant materialization: (imm32 imm64) reg.
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/// Either: movl $imm32, %reg32 or movabsq $imm64, %reg32.
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Imm_R {
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Imm {
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dst_is_64: bool,
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simm64: u64,
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dst: Writable<Reg>,
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@@ -579,31 +579,18 @@ impl Inst {
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Inst::SignExtendData { size }
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}
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pub(crate) fn imm_r(dst_is_64: bool, simm64: u64, dst: Writable<Reg>) -> Inst {
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pub(crate) fn imm(size: OperandSize, simm64: u64, dst: Writable<Reg>) -> Inst {
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debug_assert!(dst.to_reg().get_class() == RegClass::I64);
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if !dst_is_64 {
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debug_assert!(
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low32_will_sign_extend_to_64(simm64),
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"{} won't sign-extend to 64 bits!",
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simm64
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);
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}
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Inst::Imm_R {
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// Try to generate a 32-bit immediate when the upper high bits are zeroed (which matches
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// the semantics of movl).
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let dst_is_64 = size == OperandSize::Size64 && simm64 > u32::max_value() as u64;
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Inst::Imm {
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dst_is_64,
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simm64,
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dst,
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}
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}
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pub(crate) fn imm32_r_unchecked(simm64: u64, dst: Writable<Reg>) -> Inst {
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debug_assert!(dst.to_reg().get_class() == RegClass::I64);
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Inst::Imm_R {
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dst_is_64: false,
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simm64,
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dst,
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}
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}
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pub(crate) fn mov_r_r(is_64: bool, src: Reg, dst: Writable<Reg>) -> Inst {
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debug_assert!(src.get_class() == RegClass::I64);
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debug_assert!(dst.to_reg().get_class() == RegClass::I64);
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@@ -1424,7 +1411,7 @@ impl ShowWithRRU for Inst {
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show_ireg_sized(dst.to_reg(), mb_rru, dst_size.to_bytes()),
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),
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Inst::Imm_R {
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Inst::Imm {
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dst_is_64,
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simm64,
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dst,
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@@ -1761,7 +1748,7 @@ fn x64_get_regs(inst: &Inst, collector: &mut RegUsageCollector) {
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src.get_regs_as_uses(collector);
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collector.add_use(*dst);
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}
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Inst::Imm_R { dst, .. } => {
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Inst::Imm { dst, .. } => {
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collector.add_def(*dst);
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}
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Inst::Mov_R_R { src, dst, .. } | Inst::XmmToGpr { src, dst, .. } => {
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@@ -2097,7 +2084,7 @@ fn x64_map_regs<RUM: RegUsageMapper>(inst: &mut Inst, mapper: &RUM) {
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src.map_uses(mapper);
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map_use(mapper, dst);
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}
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Inst::Imm_R { ref mut dst, .. } => map_def(mapper, dst),
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Inst::Imm { ref mut dst, .. } => map_def(mapper, dst),
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Inst::Mov_R_R {
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ref mut src,
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ref mut dst,
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@@ -2407,7 +2394,57 @@ impl MachInst for Inst {
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mut alloc_tmp: F,
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) -> SmallVec<[Self; 4]> {
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let mut ret = SmallVec::new();
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if ty.is_int() {
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if ty == types::F32 {
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if value == 0 {
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ret.push(Inst::xmm_rm_r(
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SseOpcode::Xorps,
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RegMem::reg(to_reg.to_reg()),
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to_reg,
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));
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} else {
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let tmp = alloc_tmp(RegClass::I64, types::I32);
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ret.push(Inst::imm(OperandSize::Size32, value, tmp));
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ret.push(Inst::gpr_to_xmm(
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SseOpcode::Movd,
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RegMem::reg(tmp.to_reg()),
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OperandSize::Size32,
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to_reg,
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));
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}
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} else if ty == types::F64 {
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if value == 0 {
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ret.push(Inst::xmm_rm_r(
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SseOpcode::Xorpd,
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RegMem::reg(to_reg.to_reg()),
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to_reg,
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));
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} else {
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let tmp = alloc_tmp(RegClass::I64, types::I64);
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ret.push(Inst::imm(OperandSize::Size64, value, tmp));
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ret.push(Inst::gpr_to_xmm(
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SseOpcode::Movq,
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RegMem::reg(tmp.to_reg()),
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OperandSize::Size64,
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to_reg,
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));
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}
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} else {
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// Must be an integer type.
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debug_assert!(
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ty == types::B1
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|| ty == types::I8
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|| ty == types::B8
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|| ty == types::I16
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|| ty == types::B16
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|| ty == types::I32
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|| ty == types::B32
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|| ty == types::I64
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|| ty == types::B64
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|| ty == types::R32
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|| ty == types::R64
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);
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if value == 0 {
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ret.push(Inst::alu_rmi_r(
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ty == types::I64,
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@@ -2416,42 +2453,11 @@ impl MachInst for Inst {
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to_reg,
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));
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} else {
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let is_64 = ty == types::I64 && value > 0x7fffffff;
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ret.push(Inst::imm_r(is_64, value, to_reg));
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}
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} else if value == 0 {
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ret.push(Inst::xmm_rm_r(
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SseOpcode::Xorps,
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RegMem::reg(to_reg.to_reg()),
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to_reg,
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));
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} else {
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match ty {
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types::F32 => {
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let tmp = alloc_tmp(RegClass::I64, types::I32);
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ret.push(Inst::imm32_r_unchecked(value, tmp));
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ret.push(Inst::gpr_to_xmm(
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SseOpcode::Movd,
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RegMem::reg(tmp.to_reg()),
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OperandSize::Size32,
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to_reg,
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));
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}
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types::F64 => {
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let tmp = alloc_tmp(RegClass::I64, types::I64);
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ret.push(Inst::imm_r(true, value, tmp));
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ret.push(Inst::gpr_to_xmm(
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SseOpcode::Movq,
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RegMem::reg(tmp.to_reg()),
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OperandSize::Size64,
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to_reg,
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));
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}
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_ => panic!("unexpected type {:?} in gen_constant", ty),
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ret.push(Inst::imm(
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OperandSize::from_bytes(ty.bytes()),
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value,
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to_reg,
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));
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}
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}
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ret
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