riscv64: Move is_null/is_invalid to ISLE (#5874)

* riscv64: Move `is_null`/`is_invalid` to ISLE

* riscv64: Fix `is_invalid` codegen

* Implement review suggestions

Thanks!

Co-authored-by: Jamey Sharp <jamey@minilop.net>

---------

Co-authored-by: Jamey Sharp <jamey@minilop.net>

cranelift/codegen/src/isa/riscv64/inst.isle

@@ -205,11 +205,6 @@
       (x ValueRegs)
       (y ValueRegs))
 
-    (ReferenceCheck
-      (rd WritableReg)
-      (op ReferenceCheckOP)
-      (x Reg))
-
     (BrTable
       (index Reg)
       (tmp1 WritableReg)
@@ -370,11 +365,6 @@
   (Umin)
 ))
 
-(type ReferenceCheckOP (enum
-  (IsNull)
-  (IsInvalid)
-))
-
 (type AtomicOP (enum
   (LrW)
   (ScW)
@@ -879,6 +869,17 @@
 (rule (select_addi (fits_in_64 ty)) (AluOPRRI.Addi))
 
 
+;; Helper for emiting the `sltiu` instruction
+(decl sltiu (Reg Imm12) Reg)
+(rule (sltiu r imm)
+  (alu_rr_imm12 (AluOPRRI.SltiU) r imm))
+
+;; Helper for emiting the `seqz` mnemonic
+(decl seqz (Reg) Reg)
+(rule (seqz r)
+  (sltiu r (imm12_const 1)))
+
+
 (decl bnot_128 (ValueRegs) ValueRegs)
 (rule
   (bnot_128 val)
@@ -1699,14 +1700,6 @@
 (decl gen_moves (ValueRegs Type Type) ValueRegs)
 (extern constructor gen_moves gen_moves)
 
-;;
-(decl gen_reference_check (ReferenceCheckOP Reg) Reg)
-(rule
-  (gen_reference_check op r)
-  (let
-    ((tmp WritableReg (temp_writable_reg $I64))
-      (_ Unit (emit (MInst.ReferenceCheck tmp op r))))
-    tmp))
 
 ;;
 (decl gen_select (Type Reg ValueRegs ValueRegs) ValueRegs)