Add ISA-dependent settings for RISC-V.

meta/isa/riscv/recipes.py

@@ -18,27 +18,33 @@ from cretonne.formats import Binary
 # Encbits for the 32-bit recipes are opcode[6:2] | (funct3 << 5) | ...
 # The functions below encode the encbits.
 
+
 def LOAD(funct3):
     assert funct3 <= 0b111
     return 0b00000 | (funct3 << 5)
 
+
 def STORE(funct3):
     assert funct3 <= 0b111
     return 0b01000 | (funct3 << 5)
 
+
 def BRANCH(funct3):
     assert funct3 <= 0b111
     return 0b11000 | (funct3 << 5)
 
+
 def OPIMM(funct3):
     assert funct3 <= 0b111
     return 0b00100 | (funct3 << 5)
 
+
 def OP(funct3, funct7):
     assert funct3 <= 0b111
     assert funct7 <= 0b1111111
     return 0b01100 | (funct3 << 5) | (funct7 << 8)
 
+
 # R-type 32-bit instructions: These are mostly binary arithmetic instructions.
 # The encbits are `opcode[6:2] | (funct3 << 5) | (funct7 << 8)
 R = EncRecipe('R', Binary)