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Legalize fcvt_to_sint_sat.i32x4 on x86

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Use a lengthy sequence involving CVTTPS2DQ to quiet NaNs and saturate overflow.
This commit is contained in:
Andrew Brown
2020-05-26 17:14:50 -07:00
parent 3740772176
commit 3675f95bb2
4 changed files with 80 additions and 0 deletions
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15
cranelift/filetests/filetests/isa/x86/simd-conversion-legalize.clif
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@@ -17,3 +17,18 @@ block0(v0:i32x4):
; nextln: v1 = fadd v10, v7
return v1
}
function %fcvt_to_sint_sat(f32x4) -> i32x4 {
block0(v0:f32x4):
v1 = fcvt_to_sint_sat.i32x4 v0
; check: v2 = fcmp eq v0, v0
; nextln: v3 = raw_bitcast.f32x4 v2
; nextln: v4 = band v0, v3
; nextln: v5 = bxor v3, v0
; nextln: v6 = raw_bitcast.i32x4 v5
; nextln: v7 = x86_cvtt2si.i32x4 v4
; nextln: v8 = band v6, v7
; nextln: v9 = sshr_imm v8, 31
; nextln: v1 = bxor v7, v9
return v1
}

8
cranelift/filetests/filetests/isa/x86/simd-conversion-run.clif
View File

@@ -20,3 +20,11 @@ block0(v0:i32x4):
return v1
}
; run: %fcvt_from_uint([0 0 0 0]) == [0x0.0 0x0.0 0x0.0 0x0.0]
function %fcvt_to_sint_sat(f32x4) -> i32x4 {
block0(v0:f32x4):
v1 = fcvt_to_sint_sat.i32x4 v0
return v1
}
; run: %fcvt_to_sint_sat([0x0.0 -0x1.0 0x1.0 0x1.0p100]) == [0 -1 1 0x7FFFFFFF]
; run: %fcvt_to_sint_sat([-0x8.1 0x0.0 0x0.0 -0x1.0p100]) == [-8 0 0 0x80000000]