diff --git a/cranelift/codegen/src/isa/s390x/inst.isle b/cranelift/codegen/src/isa/s390x/inst.isle index 377a68e7dd..62c522dd1a 100644 --- a/cranelift/codegen/src/isa/s390x/inst.isle +++ b/cranelift/codegen/src/isa/s390x/inst.isle @@ -679,7 +679,6 @@ (type BoxCallInfo (primitive BoxCallInfo)) (type BoxCallIndInfo (primitive BoxCallIndInfo)) (type MachLabel (primitive MachLabel)) -(type VecMachLabel (primitive VecMachLabel)) (type BoxJTSequenceInfo (primitive BoxJTSequenceInfo)) (type BoxExternalName (primitive BoxExternalName)) (type ValueLabel (primitive ValueLabel)) @@ -1040,6 +1039,19 @@ (extern extractor unsigned unsigned) +;; Helpers for machine label vectors ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;; VecMachLabel needs to be passed by reference, so it cannot be +;; declared as primitive type. Declare as extern enum instead. +(type VecMachLabel extern (enum)) + +(decl vec_length_minus1 (VecMachLabel) u32) +(extern constructor vec_length_minus1 vec_length_minus1) + +(decl vec_element (VecMachLabel u8) MachLabel) +(extern constructor vec_element vec_element) + + ;; Helpers for memory arguments ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; Accessors for `RelocDistance`. @@ -1284,6 +1296,8 @@ ;; implementation detail by helpers that preserve the SSA facade themselves. (decl emit (MInst) Unit) (extern constructor emit emit) +(decl emit_safepoint (MInst) Unit) +(extern constructor emit_safepoint emit_safepoint) ;; Helper for emitting `MInst.AluRRR` instructions. (decl alu_rrr (Type ALUOp Reg Reg) Reg) @@ -1695,6 +1709,26 @@ (_ Unit (emit (MInst.LoadAddr dst mem)))) (writable_reg_to_reg dst))) +;; Helper for emitting `MInst.Jump` instructions. +(decl jump_impl (MachLabel) SideEffectNoResult) +(rule (jump_impl target) + (SideEffectNoResult.Inst (MInst.Jump target))) + +;; Helper for emitting `MInst.CondBr` instructions. +(decl cond_br (MachLabel MachLabel Cond) SideEffectNoResult) +(rule (cond_br taken not_taken cond) + (SideEffectNoResult.Inst (MInst.CondBr taken not_taken cond))) + +;; Helper for emitting `MInst.OneWayCondBr` instructions. +(decl oneway_cond_br (MachLabel Cond) SideEffectNoResult) +(rule (oneway_cond_br dest cond) + (SideEffectNoResult.Inst (MInst.OneWayCondBr dest cond))) + +;; Helper for emitting `MInst.JTSequence` instructions. +(decl jt_sequence (Reg VecMachLabel) SideEffectNoResult) +(rule (jt_sequence ridx targets) + (SideEffectNoResult.Inst (MInst.JTSequence ridx targets))) + ;; Emit a `ProducesFlags` instruction when the flags are not actually needed. (decl drop_flags (ProducesFlags) Reg) (rule (drop_flags (ProducesFlags.ProducesFlags inst result)) @@ -2149,6 +2183,23 @@ src imm cond trap_code)))) (invalid_reg))) +(decl trap_impl (TrapCode) SideEffectNoResult) +(rule (trap_impl trap_code) + (SideEffectNoResult.Inst (MInst.Trap trap_code))) + +(decl trap_if_impl (Cond TrapCode) SideEffectNoResult) +(rule (trap_if_impl cond trap_code) + (SideEffectNoResult.Inst (MInst.TrapIf cond trap_code))) + +(decl debugtrap_impl () SideEffectNoResult) +(rule (debugtrap_impl) + (SideEffectNoResult.Inst (MInst.Debugtrap))) + +(decl safepoint (SideEffectNoResult) ValueRegs) +(rule (safepoint (SideEffectNoResult.Inst inst)) + (let ((_ Unit (emit_safepoint inst))) + (value_regs_invalid))) + ;; Helpers for handling boolean conditions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -2201,6 +2252,24 @@ (rule (lower_bool $B32 cond) (select_bool_imm $B32 cond -1 0)) (rule (lower_bool $B64 cond) (select_bool_imm $B64 cond -1 0)) +;; Emit a conditional branch based on a boolean condition. +(decl cond_br_bool (ProducesBool MachLabel MachLabel) SideEffectNoResult) +(rule (cond_br_bool (ProducesBool.ProducesBool producer cond) taken not_taken) + (let ((_ Unit (emit_producer producer))) + (cond_br taken not_taken cond))) + +;; Emit a one-way conditional branch based on a boolean condition. +(decl oneway_cond_br_bool (ProducesBool MachLabel) SideEffectNoResult) +(rule (oneway_cond_br_bool (ProducesBool.ProducesBool producer cond) dest) + (let ((_ Unit (emit_producer producer))) + (oneway_cond_br dest cond))) + +;; Emit a conditional trap based on a boolean condition. +(decl trap_if_bool (ProducesBool TrapCode) SideEffectNoResult) +(rule (trap_if_bool (ProducesBool.ProducesBool producer cond) trap_code) + (let ((_ Unit (emit_producer producer))) + (trap_if_impl cond trap_code))) + ;; Helpers for generating `clz` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/cranelift/codegen/src/isa/s390x/lower.isle b/cranelift/codegen/src/isa/s390x/lower.isle index ae464c5cc9..dbd24fbdf0 100644 --- a/cranelift/codegen/src/isa/s390x/lower.isle +++ b/cranelift/codegen/src/isa/s390x/lower.isle @@ -4,6 +4,11 @@ ;; register(s) within which the lowered instruction's result values live. (decl lower (Inst) ValueRegs) +;; A variant of the main lowering constructor term, used for branches. +;; The only difference is that it gets an extra argument holding a vector +;; of branch targets to be used. +(decl lower_branch (Inst VecMachLabel) ValueRegs) + ;;;; Rules for `iconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -1778,3 +1783,151 @@ (value_reg (select_bool_reg ty (icmp_val $false int_cc x y) (put_in_reg val_true) (put_in_reg val_false)))) + +;;;; Rules for `jump` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;; Unconditional branch. The target is found as first (and only) element in +;; the list of the current block's branch targets passed as `targets`. +(rule (lower_branch (jump _ _) targets) + (value_regs_none (jump_impl (vec_element targets 0)))) + + +;;;; Rules for `br_table` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;; Jump table. `targets` contains the default target followed by the +;; list of branch targets per index value. +(rule (lower_branch (br_table val_idx _ _) targets) + (let ((idx Reg (put_in_reg_zext64 val_idx)) + ;; Bounds-check the index and branch to default. + ;; This is an internal branch that is not a terminator insn. + ;; Instead, the default target is listed a potential target + ;; in the final JTSequence, which is the block terminator. + (cond ProducesBool + (bool (icmpu_uimm32 $I64 idx (vec_length_minus1 targets)) + (intcc_as_cond (IntCC.UnsignedGreaterThanOrEqual)))) + (_ ValueRegs (value_regs_none (oneway_cond_br_bool cond + (vec_element targets 0))))) + ;; Scale the index by the element size, and then emit the + ;; compound instruction that does: + ;; + ;; larl %r1, + ;; agf %r1, 0(%r1, %rScaledIndex) + ;; br %r1 + ;; [jt entries] + ;; + ;; This must be *one* instruction in the vcode because + ;; we cannot allow regalloc to insert any spills/fills + ;; in the middle of the sequence; otherwise, the LARL's + ;; PC-rel offset to the jumptable would be incorrect. + ;; (The alternative is to introduce a relocation pass + ;; for inlined jumptables, which is much worse, IMHO.) + (value_regs_none (jt_sequence (lshl_imm $I64 idx 2) targets)))) + + +;;;; Rules for `brz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;; Two-way conditional branch on zero. `targets` contains: +;; - element 0: target if the condition is true (i.e. value is zero) +;; - element 1: target if the condition is false (i.e. value is nonzero) +(rule (lower_branch (brz val_cond _ _) targets) + (value_regs_none (cond_br_bool (invert_bool (value_nonzero val_cond)) + (vec_element targets 0) + (vec_element targets 1)))) + + +;;;; Rules for `brnz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;; Two-way conditional branch on nonzero. `targets` contains: +;; - element 0: target if the condition is true (i.e. value is nonzero) +;; - element 1: target if the condition is false (i.e. value is zero) +(rule (lower_branch (brnz val_cond _ _) targets) + (value_regs_none (cond_br_bool (value_nonzero val_cond) + (vec_element targets 0) + (vec_element targets 1)))) + + +;;;; Rules for `brif` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;; Similarly to `selectif_spectre_guard`, we only recognize specific patterns +;; generated by common code here. Others will fail to lower. + +(rule (lower_branch (brif int_cc (def_inst (ifcmp x y)) _ _) targets) + (value_regs_none (cond_br_bool (icmp_val $false int_cc x y) + (vec_element targets 0) + (vec_element targets 1)))) + + +;;;; Rules for `trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(rule (lower (trap trap_code)) + (safepoint (trap_impl trap_code))) + + +;;;; Rules for `resumable_trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(rule (lower (resumable_trap trap_code)) + (safepoint (trap_impl trap_code))) + + +;;;; Rules for `trapz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(rule (lower (trapz val trap_code)) + (safepoint (trap_if_bool (invert_bool (value_nonzero val)) trap_code))) + + +;;;; Rules for `trapnz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(rule (lower (trapnz val trap_code)) + (safepoint (trap_if_bool (value_nonzero val) trap_code))) + + +;;;; Rules for `resumable_trapnz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(rule (lower (resumable_trapnz val trap_code)) + (safepoint (trap_if_bool (value_nonzero val) trap_code))) + + +;;;; Rules for `debugtrap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(rule (lower (debugtrap)) + (value_regs_none (debugtrap_impl))) + + +;;;; Rules for `trapif` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;; Similarly to `selectif_spectre_guard`, we only recognize specific patterns +;; generated by common code here. Others will fail to lower. + +;; Recognize the case of `ifcmp` feeding into `trapif`. Directly generate +;; the desired comparison here; there is no separate `ifcmp` lowering. + +(rule (lower (trapif int_cc (def_inst (ifcmp x y)) trap_code)) + (safepoint (trap_if_bool (icmp_val $false int_cc x y) trap_code))) + +;; Recognize the case of `iadd_ifcout` feeding into `trapif`. Note that +;; in the case, the `iadd_ifcout` is generated by a separate lowering +;; (in order to properly handle the register output of that instruction.) +;; +;; The flags must not have been clobbered by any other instruction between the +;; iadd_ifcout and this instruction, as verified by the CLIF validator; so we +;; can simply rely on the condition code here. +;; +;; IaddIfcout is implemented via a ADD LOGICAL instruction, which sets the +;; the condition code as follows: +;; 0 Result zero; no carry +;; 1 Result not zero; no carry +;; 2 Result zero; carry +;; 3 Result not zero; carry +;; This means "carry" corresponds to condition code 2 or 3, i.e. +;; a condition mask of 2 | 1. +;; +;; As this does not match any of the encodings used with a normal integer +;; comparsion, this cannot be represented by any IntCC value. We need to +;; remap the IntCC::UnsignedGreaterThan value that we have here as result +;; of the unsigned_add_overflow_condition call to the correct mask. + +(rule (lower (trapif (IntCC.UnsignedGreaterThan) + (def_inst (iadd_ifcout x y)) trap_code)) + (value_regs_none (trap_if_impl (mask_as_cond 3) trap_code))) + + diff --git a/cranelift/codegen/src/isa/s390x/lower.rs b/cranelift/codegen/src/isa/s390x/lower.rs index df966b79c2..2f181478f5 100644 --- a/cranelift/codegen/src/isa/s390x/lower.rs +++ b/cranelift/codegen/src/isa/s390x/lower.rs @@ -2,7 +2,7 @@ use crate::ir::condcodes::IntCC; use crate::ir::Inst as IRInst; -use crate::ir::{types, Endianness, MemFlags, Opcode, Type}; +use crate::ir::{MemFlags, Opcode}; use crate::isa::s390x::abi::*; use crate::isa::s390x::inst::*; use crate::isa::s390x::settings as s390x_settings; @@ -11,255 +11,14 @@ use crate::machinst::lower::*; use crate::machinst::*; use crate::settings::Flags; use crate::CodegenResult; -use alloc::boxed::Box; -use core::convert::TryFrom; -use regalloc::{Reg, Writable}; +use regalloc::Reg; use smallvec::SmallVec; pub mod isle; -//============================================================================= -// Helpers for instruction lowering. - -fn choose_32_64(ty: Type, op32: T, op64: T) -> T { - let bits = ty_bits(ty); - if bits <= 32 { - op32 - } else if bits == 64 { - op64 - } else { - panic!("choose_32_64 on > 64 bits!") - } -} - -//============================================================================ -// Lowering: convert instruction inputs to forms that we can use. - -/// Lower an instruction input to a 64-bit constant, if possible. -fn input_matches_const>(ctx: &mut C, input: InsnInput) -> Option { - let input = ctx.get_input_as_source_or_const(input.insn, input.input); - input.constant -} - -/// Lower an instruction input to a 64-bit signed constant, if possible. -fn input_matches_sconst>(ctx: &mut C, input: InsnInput) -> Option { - if let Some(imm) = input_matches_const(ctx, input) { - let ty = ctx.input_ty(input.insn, input.input); - Some(sign_extend_to_u64(imm, ty_bits(ty) as u8) as i64) - } else { - None - } -} - -/// Lower an instruction input to a 16-bit signed constant, if possible. -fn input_matches_simm16>(ctx: &mut C, input: InsnInput) -> Option { - if let Some(imm_value) = input_matches_sconst(ctx, input) { - if let Ok(imm) = i16::try_from(imm_value) { - return Some(imm); - } - } - None -} - -/// Lower an instruction input to a 32-bit signed constant, if possible. -fn input_matches_simm32>(ctx: &mut C, input: InsnInput) -> Option { - if let Some(imm_value) = input_matches_sconst(ctx, input) { - if let Ok(imm) = i32::try_from(imm_value) { - return Some(imm); - } - } - None -} - -/// Lower an instruction input to a 32-bit unsigned constant, if possible. -fn input_matches_uimm32>(ctx: &mut C, input: InsnInput) -> Option { - if let Some(imm_value) = input_matches_const(ctx, input) { - if let Ok(imm) = u32::try_from(imm_value) { - return Some(imm); - } - } - None -} - -/// Checks for an instance of `op` feeding the given input. -fn input_matches_insn>( - c: &mut C, - input: InsnInput, - op: Opcode, -) -> Option { - let inputs = c.get_input_as_source_or_const(input.insn, input.input); - if let Some((src_inst, _)) = inputs.inst { - let data = c.data(src_inst); - if data.opcode() == op { - return Some(src_inst); - } - } - None -} - -/// Checks for an instance of `op` feeding the given input, possibly via a conversion `conv` (e.g., -/// Bint or a bitcast). -fn input_matches_insn_via_conv>( - c: &mut C, - input: InsnInput, - op: Opcode, - conv: Opcode, -) -> Option { - let inputs = c.get_input_as_source_or_const(input.insn, input.input); - if let Some((src_inst, _)) = inputs.inst { - let data = c.data(src_inst); - if data.opcode() == op { - return Some(src_inst); - } - if data.opcode() == conv { - let inputs = c.get_input_as_source_or_const(src_inst, 0); - if let Some((src_inst, _)) = inputs.inst { - let data = c.data(src_inst); - if data.opcode() == op { - return Some(src_inst); - } - } - } - } - None -} - -fn input_matches_load_insn>( - ctx: &mut C, - input: InsnInput, - op: Opcode, -) -> Option { - if let Some(insn) = input_matches_insn(ctx, input, op) { - let inputs: SmallVec<[InsnInput; 4]> = (0..ctx.num_inputs(insn)) - .map(|i| InsnInput { insn, input: i }) - .collect(); - let off = ctx.data(insn).load_store_offset().unwrap(); - let flags = ctx.memflags(insn).unwrap(); - let endianness = flags.endianness(Endianness::Big); - if endianness == Endianness::Big { - let mem = lower_address(ctx, &inputs[..], off, flags); - ctx.sink_inst(insn); - return Some(mem); - } - } - None -} - -fn input_matches_mem>(ctx: &mut C, input: InsnInput) -> Option { - if ty_bits(ctx.input_ty(input.insn, input.input)) >= 32 { - return input_matches_load_insn(ctx, input, Opcode::Load); - } - None -} - -fn input_matches_sext16_mem>( - ctx: &mut C, - input: InsnInput, -) -> Option { - if ty_bits(ctx.input_ty(input.insn, input.input)) == 16 { - return input_matches_load_insn(ctx, input, Opcode::Load); - } - if ty_bits(ctx.input_ty(input.insn, input.input)) >= 32 { - return input_matches_load_insn(ctx, input, Opcode::Sload16); - } - None -} - -fn input_matches_sext32_mem>( - ctx: &mut C, - input: InsnInput, -) -> Option { - if ty_bits(ctx.input_ty(input.insn, input.input)) > 32 { - return input_matches_load_insn(ctx, input, Opcode::Sload32); - } - None -} - -fn input_matches_sext32_reg>(ctx: &mut C, input: InsnInput) -> Option { - if let Some(insn) = input_matches_insn(ctx, input, Opcode::Sextend) { - if ty_bits(ctx.input_ty(insn, 0)) == 32 { - let reg = put_input_in_reg(ctx, InsnInput { insn, input: 0 }, NarrowValueMode::None); - return Some(reg); - } - } - None -} - -fn input_matches_uext32_reg>(ctx: &mut C, input: InsnInput) -> Option { - if let Some(insn) = input_matches_insn(ctx, input, Opcode::Uextend) { - if ty_bits(ctx.input_ty(insn, 0)) == 32 { - let reg = put_input_in_reg(ctx, InsnInput { insn, input: 0 }, NarrowValueMode::None); - return Some(reg); - } - } - None -} - -fn input_matches_uext16_mem>( - ctx: &mut C, - input: InsnInput, -) -> Option { - if ty_bits(ctx.input_ty(input.insn, input.input)) == 16 { - return input_matches_load_insn(ctx, input, Opcode::Load); - } - if ty_bits(ctx.input_ty(input.insn, input.input)) >= 32 { - return input_matches_load_insn(ctx, input, Opcode::Uload16); - } - None -} - -fn input_matches_uext32_mem>( - ctx: &mut C, - input: InsnInput, -) -> Option { - if ty_bits(ctx.input_ty(input.insn, input.input)) > 32 { - return input_matches_load_insn(ctx, input, Opcode::Uload32); - } - None -} - //============================================================================ // Lowering: force instruction input into a register -/// How to handle narrow values loaded into registers; see note on `narrow_mode` -/// parameter to `put_input_in_*` below. -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -enum NarrowValueMode { - None, - /// Zero-extend to 32 bits if original is < 32 bits. - ZeroExtend32, - /// Sign-extend to 32 bits if original is < 32 bits. - SignExtend32, - /// Zero-extend to 64 bits if original is < 64 bits. - ZeroExtend64, - /// Sign-extend to 64 bits if original is < 64 bits. - SignExtend64, -} - -fn extend_memory_to_reg>( - ctx: &mut C, - mem: MemArg, - from_ty: Type, - to_ty: Type, - signed: bool, -) -> Reg { - let rd = ctx.alloc_tmp(to_ty).only_reg().unwrap(); - ctx.emit(match (signed, ty_bits(to_ty), ty_bits(from_ty)) { - (false, 32, 8) => Inst::Load32ZExt8 { rd, mem }, - (false, 32, 16) => Inst::Load32ZExt16 { rd, mem }, - (true, 32, 8) => Inst::Load32SExt8 { rd, mem }, - (true, 32, 16) => Inst::Load32SExt16 { rd, mem }, - (false, 64, 8) => Inst::Load64ZExt8 { rd, mem }, - (false, 64, 16) => Inst::Load64ZExt16 { rd, mem }, - (false, 64, 32) => Inst::Load64ZExt32 { rd, mem }, - (true, 64, 8) => Inst::Load64SExt8 { rd, mem }, - (true, 64, 16) => Inst::Load64SExt16 { rd, mem }, - (true, 64, 32) => Inst::Load64SExt32 { rd, mem }, - _ => panic!("Unsupported size in load"), - }); - rd.to_reg() -} - /// Sign-extend the low `from_bits` bits of `value` to a full u64. fn sign_extend_to_u64(value: u64, from_bits: u8) -> u64 { assert!(from_bits <= 64); @@ -270,169 +29,11 @@ fn sign_extend_to_u64(value: u64, from_bits: u8) -> u64 { } } -/// Zero-extend the low `from_bits` bits of `value` to a full u64. -fn zero_extend_to_u64(value: u64, from_bits: u8) -> u64 { - assert!(from_bits <= 64); - if from_bits >= 64 { - value - } else { - value & ((1u64 << from_bits) - 1) - } -} - /// Lower an instruction input to a reg. -/// -/// The given register will be extended appropriately, according to -/// `narrow_mode` and the input's type. -fn put_input_in_reg>( - ctx: &mut C, - input: InsnInput, - narrow_mode: NarrowValueMode, -) -> Reg { - let signed = match narrow_mode { - NarrowValueMode::SignExtend32 | NarrowValueMode::SignExtend64 => true, - NarrowValueMode::ZeroExtend32 | NarrowValueMode::ZeroExtend64 => false, - _ => false, - }; - let ty = ctx.input_ty(input.insn, input.input); - let from_bits = ty_bits(ty) as u8; - let ext_ty = match narrow_mode { - NarrowValueMode::None => ty, - NarrowValueMode::ZeroExtend32 | NarrowValueMode::SignExtend32 => types::I32, - NarrowValueMode::ZeroExtend64 | NarrowValueMode::SignExtend64 => types::I64, - }; - let to_bits = ty_bits(ext_ty) as u8; - assert!(to_bits >= from_bits); - - if let Some(c) = input_matches_const(ctx, input) { - let extended = if from_bits == to_bits { - c - } else if signed { - sign_extend_to_u64(c, from_bits) - } else { - zero_extend_to_u64(c, from_bits) - }; - let masked = zero_extend_to_u64(extended, to_bits); - - // Generate constants fresh at each use to minimize long-range register pressure. - let to_reg = ctx.alloc_tmp(ext_ty).only_reg().unwrap(); - for inst in Inst::gen_constant(ValueRegs::one(to_reg), masked as u128, ext_ty, |ty| { - ctx.alloc_tmp(ty).only_reg().unwrap() - }) - .into_iter() - { - ctx.emit(inst); - } - to_reg.to_reg() - } else if to_bits == from_bits { - ctx.put_input_in_regs(input.insn, input.input) - .only_reg() - .unwrap() - } else if let Some(mem) = input_matches_load_insn(ctx, input, Opcode::Load) { - extend_memory_to_reg(ctx, mem, ty, ext_ty, signed) - } else { - let rd = ctx.alloc_tmp(ext_ty).only_reg().unwrap(); - let rn = ctx - .put_input_in_regs(input.insn, input.input) - .only_reg() - .unwrap(); - ctx.emit(Inst::Extend { - rd, - rn, - signed, - from_bits, - to_bits, - }); - rd.to_reg() - } -} - -//============================================================================ -// Lowering: addressing mode support. Takes instruction directly, rather -// than an `InsnInput`, to do more introspection. - -/// Lower the address of a load or store. -fn lower_address>( - ctx: &mut C, - addends: &[InsnInput], - offset: i32, - flags: MemFlags, -) -> MemArg { - // Handle one reg and offset. - if addends.len() == 1 { - if offset == 0 { - if let Some(add) = input_matches_insn(ctx, addends[0], Opcode::Iadd) { - debug_assert_eq!(ctx.output_ty(add, 0), types::I64); - let add_inputs = &[ - InsnInput { - insn: add, - input: 0, - }, - InsnInput { - insn: add, - input: 1, - }, - ]; - - let ra = put_input_in_reg(ctx, add_inputs[0], NarrowValueMode::None); - let rb = put_input_in_reg(ctx, add_inputs[1], NarrowValueMode::None); - return MemArg::reg_plus_reg(ra, rb, flags); - } - } - - if let Some(symbol) = input_matches_insn(ctx, addends[0], Opcode::SymbolValue) { - let (extname, dist, ext_offset) = ctx.symbol_value(symbol).unwrap(); - let ext_offset = ext_offset + i64::from(offset); - if dist == RelocDistance::Near && (ext_offset & 1) == 0 { - if let Ok(offset) = i32::try_from(ext_offset) { - return MemArg::Symbol { - name: Box::new(extname.clone()), - offset, - flags, - }; - } - } - } - - let reg = put_input_in_reg(ctx, addends[0], NarrowValueMode::None); - return MemArg::reg_plus_off(reg, offset as i64, flags); - } - - // Handle two regs and a zero offset. - if addends.len() == 2 && offset == 0 { - let ra = put_input_in_reg(ctx, addends[0], NarrowValueMode::None); - let rb = put_input_in_reg(ctx, addends[1], NarrowValueMode::None); - return MemArg::reg_plus_reg(ra, rb, flags); - } - - // Otherwise, generate add instructions. - let addr = ctx.alloc_tmp(types::I64).only_reg().unwrap(); - - // Get the const into a reg. - lower_constant_u64(ctx, addr.clone(), offset as u64); - - // Add each addend to the address. - for addend in addends { - let reg = put_input_in_reg(ctx, *addend, NarrowValueMode::None); - - ctx.emit(Inst::AluRRR { - alu_op: ALUOp::Add64, - rd: addr.clone(), - rn: addr.to_reg(), - rm: reg.clone(), - }); - } - - MemArg::reg(addr.to_reg(), flags) -} - -//============================================================================ -// Lowering: generating constants. - -fn lower_constant_u64>(ctx: &mut C, rd: Writable, value: u64) { - for inst in Inst::load_constant64(rd, value) { - ctx.emit(inst); - } +fn put_input_in_reg>(ctx: &mut C, input: InsnInput) -> Reg { + ctx.put_input_in_regs(input.insn, input.input) + .only_reg() + .unwrap() } //============================================================================= @@ -459,151 +60,6 @@ pub fn condcode_is_signed(cc: IntCC) -> bool { } } -fn lower_icmp_to_flags>( - ctx: &mut C, - insn: IRInst, - is_signed: bool, - may_sink_memory: bool, -) { - let ty = ctx.input_ty(insn, 0); - let bits = ty_bits(ty); - let narrow_mode = match (bits <= 32, is_signed) { - (true, true) => NarrowValueMode::SignExtend32, - (true, false) => NarrowValueMode::ZeroExtend32, - (false, true) => NarrowValueMode::SignExtend64, - (false, false) => NarrowValueMode::ZeroExtend64, - }; - let inputs = [InsnInput { insn, input: 0 }, InsnInput { insn, input: 1 }]; - let ty = ctx.input_ty(insn, 0); - let rn = put_input_in_reg(ctx, inputs[0], narrow_mode); - if is_signed { - let op = choose_32_64(ty, CmpOp::CmpS32, CmpOp::CmpS64); - // Try matching immedate operand. - if let Some(imm) = input_matches_simm16(ctx, inputs[1]) { - return ctx.emit(Inst::CmpRSImm16 { op, rn, imm }); - } - if let Some(imm) = input_matches_simm32(ctx, inputs[1]) { - return ctx.emit(Inst::CmpRSImm32 { op, rn, imm }); - } - // If sinking memory loads is allowed, try matching memory operand. - if may_sink_memory { - if let Some(mem) = input_matches_mem(ctx, inputs[1]) { - return ctx.emit(Inst::CmpRX { op, rn, mem }); - } - if let Some(mem) = input_matches_sext16_mem(ctx, inputs[1]) { - let op = choose_32_64(ty, CmpOp::CmpS32Ext16, CmpOp::CmpS64Ext16); - return ctx.emit(Inst::CmpRX { op, rn, mem }); - } - if let Some(mem) = input_matches_sext32_mem(ctx, inputs[1]) { - return ctx.emit(Inst::CmpRX { - op: CmpOp::CmpS64Ext32, - rn, - mem, - }); - } - } - // Try matching sign-extension in register. - if let Some(rm) = input_matches_sext32_reg(ctx, inputs[1]) { - return ctx.emit(Inst::CmpRR { - op: CmpOp::CmpS64Ext32, - rn, - rm, - }); - } - // If no special case matched above, fall back to a register compare. - let rm = put_input_in_reg(ctx, inputs[1], narrow_mode); - return ctx.emit(Inst::CmpRR { op, rn, rm }); - } else { - let op = choose_32_64(ty, CmpOp::CmpL32, CmpOp::CmpL64); - // Try matching immedate operand. - if let Some(imm) = input_matches_uimm32(ctx, inputs[1]) { - return ctx.emit(Inst::CmpRUImm32 { op, rn, imm }); - } - // If sinking memory loads is allowed, try matching memory operand. - if may_sink_memory { - if let Some(mem) = input_matches_mem(ctx, inputs[1]) { - return ctx.emit(Inst::CmpRX { op, rn, mem }); - } - if let Some(mem) = input_matches_uext16_mem(ctx, inputs[1]) { - match &mem { - &MemArg::Symbol { .. } => { - let op = choose_32_64(ty, CmpOp::CmpL32Ext16, CmpOp::CmpL64Ext16); - return ctx.emit(Inst::CmpRX { op, rn, mem }); - } - _ => { - let reg_ty = choose_32_64(ty, types::I32, types::I64); - let rm = extend_memory_to_reg(ctx, mem, types::I16, reg_ty, false); - return ctx.emit(Inst::CmpRR { op, rn, rm }); - } - } - } - if let Some(mem) = input_matches_uext32_mem(ctx, inputs[1]) { - return ctx.emit(Inst::CmpRX { - op: CmpOp::CmpL64Ext32, - rn, - mem, - }); - } - } - // Try matching zero-extension in register. - if let Some(rm) = input_matches_uext32_reg(ctx, inputs[1]) { - return ctx.emit(Inst::CmpRR { - op: CmpOp::CmpL64Ext32, - rn, - rm, - }); - } - // If no special case matched above, fall back to a register compare. - let rm = put_input_in_reg(ctx, inputs[1], narrow_mode); - return ctx.emit(Inst::CmpRR { op, rn, rm }); - } -} - -fn lower_fcmp_to_flags>(ctx: &mut C, insn: IRInst) { - let ty = ctx.input_ty(insn, 0); - let bits = ty_bits(ty); - let inputs = [InsnInput { insn, input: 0 }, InsnInput { insn, input: 1 }]; - let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None); - let rm = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None); - match bits { - 32 => { - ctx.emit(Inst::FpuCmp32 { rn, rm }); - } - 64 => { - ctx.emit(Inst::FpuCmp64 { rn, rm }); - } - _ => panic!("Unknown float size"), - } -} - -fn lower_boolean_to_flags>(ctx: &mut C, input: InsnInput) -> Cond { - if let Some(icmp_insn) = input_matches_insn_via_conv(ctx, input, Opcode::Icmp, Opcode::Bint) { - // FIXME: If the Icmp (and Bint) only have a single use, we can still allow sinking memory - let may_sink_memory = false; - let condcode = ctx.data(icmp_insn).cond_code().unwrap(); - let is_signed = condcode_is_signed(condcode); - lower_icmp_to_flags(ctx, icmp_insn, is_signed, may_sink_memory); - Cond::from_intcc(condcode) - } else if let Some(fcmp_insn) = - input_matches_insn_via_conv(ctx, input, Opcode::Fcmp, Opcode::Bint) - { - let condcode = ctx.data(fcmp_insn).fp_cond_code().unwrap(); - lower_fcmp_to_flags(ctx, fcmp_insn); - Cond::from_floatcc(condcode) - } else { - let ty = ctx.input_ty(input.insn, input.input); - let narrow_mode = if ty.bits() < 32 { - NarrowValueMode::ZeroExtend32 - } else { - NarrowValueMode::None - }; - let rn = put_input_in_reg(ctx, input, narrow_mode); - let op = choose_32_64(ty, CmpOp::CmpS32, CmpOp::CmpS64); - ctx.emit(Inst::CmpRSImm16 { op, rn, imm: 0 }); - Cond::from_intcc(IntCC::NotEqual) - } -} - //============================================================================ // Lowering: main entry point for lowering a instruction @@ -728,6 +184,13 @@ fn lower_insn_to_regs>( | Opcode::IsInvalid | Opcode::Select | Opcode::SelectifSpectreGuard + | Opcode::Trap + | Opcode::ResumableTrap + | Opcode::Trapz + | Opcode::Trapnz + | Opcode::ResumableTrapnz + | Opcode::Trapif + | Opcode::Debugtrap | Opcode::StackAddr | Opcode::FuncAddr | Opcode::SymbolValue => implemented_in_isle(), @@ -765,63 +228,6 @@ fn lower_insn_to_regs>( unimplemented!("Pinned register support not implemented!"); } - Opcode::Trap | Opcode::ResumableTrap => { - let trap_code = ctx.data(insn).trap_code().unwrap(); - ctx.emit_safepoint(Inst::Trap { trap_code }) - } - - Opcode::Trapz | Opcode::Trapnz | Opcode::ResumableTrapnz => { - let cond = lower_boolean_to_flags(ctx, inputs[0]); - let negated = op == Opcode::Trapz; - let cond = if negated { cond.invert() } else { cond }; - let trap_code = ctx.data(insn).trap_code().unwrap(); - ctx.emit_safepoint(Inst::TrapIf { trap_code, cond }); - } - - Opcode::Trapif => { - let condcode = ctx.data(insn).cond_code().unwrap(); - let mut cond = Cond::from_intcc(condcode); - let is_signed = condcode_is_signed(condcode); - - let cmp_insn = ctx - .get_input_as_source_or_const(inputs[0].insn, inputs[0].input) - .inst - .unwrap() - .0; - if ctx.data(cmp_insn).opcode() == Opcode::IaddIfcout { - // The flags must not have been clobbered by any other instruction between the - // iadd_ifcout and this instruction, as verified by the CLIF validator; so we - // can simply rely on the condition code here. - // - // IaddIfcout is implemented via a ADD LOGICAL instruction, which sets the - // the condition code as follows: - // 0 Result zero; no carry - // 1 Result not zero; no carry - // 2 Result zero; carry - // 3 Result not zero; carry - // This means "carry" corresponds to condition code 2 or 3, i.e. - // a condition mask of 2 | 1. - // - // As this does not match any of the encodings used with a normal integer - // comparsion, this cannot be represented by any IntCC value. We need to - // remap the IntCC::UnsignedGreaterThan value that we have here as result - // of the unsigned_add_overflow_condition call to the correct mask. - assert!(condcode == IntCC::UnsignedGreaterThan); - cond = Cond::from_mask(2 | 1); - } else { - // Verification ensures that the input is always a single-def ifcmp - debug_assert_eq!(ctx.data(cmp_insn).opcode(), Opcode::Ifcmp); - lower_icmp_to_flags(ctx, cmp_insn, is_signed, true); - } - - let trap_code = ctx.data(insn).trap_code().unwrap(); - ctx.emit_safepoint(Inst::TrapIf { trap_code, cond }); - } - - Opcode::Debugtrap => { - ctx.emit(Inst::Debugtrap); - } - Opcode::Call | Opcode::CallIndirect => { let caller_conv = ctx.abi().call_conv(); let (mut abi, inputs) = match op { @@ -837,7 +243,7 @@ fn lower_insn_to_regs>( ) } Opcode::CallIndirect => { - let ptr = put_input_in_reg(ctx, inputs[0], NarrowValueMode::ZeroExtend64); + let ptr = put_input_in_reg(ctx, inputs[0]); let sig = ctx.call_sig(insn).unwrap(); assert!(inputs.len() - 1 == sig.params.len()); assert!(outputs.len() == sig.returns.len()); @@ -851,7 +257,7 @@ fn lower_insn_to_regs>( assert!(inputs.len() == abi.num_args()); for (i, input) in inputs.iter().enumerate() { - let arg_reg = put_input_in_reg(ctx, *input, NarrowValueMode::None); + let arg_reg = put_input_in_reg(ctx, *input); abi.emit_copy_regs_to_arg(ctx, i, ValueRegs::one(arg_reg)); } abi.emit_call(ctx); @@ -864,7 +270,7 @@ fn lower_insn_to_regs>( Opcode::FallthroughReturn | Opcode::Return => { for (i, input) in inputs.iter().enumerate() { - let reg = put_input_in_reg(ctx, *input, NarrowValueMode::None); + let reg = put_input_in_reg(ctx, *input); let retval_reg = ctx.retval(i).only_reg().unwrap(); let ty = ctx.input_ty(insn, i); ctx.emit(Inst::gen_move(retval_reg, reg, ty)); @@ -995,146 +401,6 @@ fn lower_insn_to_regs>( Ok(()) } -//============================================================================ -// Lowering: main entry point for lowering a branch group - -fn lower_branch>( - ctx: &mut C, - branches: &[IRInst], - targets: &[MachLabel], -) -> CodegenResult<()> { - // A block should end with at most two branches. The first may be a - // conditional branch; a conditional branch can be followed only by an - // unconditional branch or fallthrough. Otherwise, if only one branch, - // it may be an unconditional branch, a fallthrough, a return, or a - // trap. These conditions are verified by `is_ebb_basic()` during the - // verifier pass. - assert!(branches.len() <= 2); - - if branches.len() == 2 { - // Must be a conditional branch followed by an unconditional branch. - let op0 = ctx.data(branches[0]).opcode(); - let op1 = ctx.data(branches[1]).opcode(); - - assert!(op1 == Opcode::Jump); - let taken = targets[0]; - let not_taken = targets[1]; - - match op0 { - Opcode::Brz | Opcode::Brnz => { - let flag_input = InsnInput { - insn: branches[0], - input: 0, - }; - let cond = lower_boolean_to_flags(ctx, flag_input); - let negated = op0 == Opcode::Brz; - let cond = if negated { cond.invert() } else { cond }; - ctx.emit(Inst::CondBr { - taken, - not_taken, - cond, - }); - } - - Opcode::Brif => { - let condcode = ctx.data(branches[0]).cond_code().unwrap(); - let cond = Cond::from_intcc(condcode); - let is_signed = condcode_is_signed(condcode); - - // Verification ensures that the input is always a single-def ifcmp. - let cmp_insn = ctx - .get_input_as_source_or_const(branches[0], 0) - .inst - .unwrap() - .0; - debug_assert_eq!(ctx.data(cmp_insn).opcode(), Opcode::Ifcmp); - lower_icmp_to_flags(ctx, cmp_insn, is_signed, true); - - ctx.emit(Inst::CondBr { - taken, - not_taken, - cond, - }); - } - - Opcode::Brff => unreachable!(), - - _ => unimplemented!(), - } - } else { - // Must be an unconditional branch or an indirect branch. - let op = ctx.data(branches[0]).opcode(); - match op { - Opcode::Jump => { - assert!(branches.len() == 1); - ctx.emit(Inst::Jump { dest: targets[0] }); - } - - Opcode::BrTable => { - let jt_size = targets.len() - 1; - assert!(jt_size <= std::u32::MAX as usize); - - // Load up jump table element index. - let ridx = put_input_in_reg( - ctx, - InsnInput { - insn: branches[0], - input: 0, - }, - NarrowValueMode::ZeroExtend64, - ); - - // Bounds-check index and branch to default. - // This is an internal branch that is not a terminator insn. - // Instead, the default target is listed a potential target - // in the final JTSequence, which is the block terminator. - ctx.emit(Inst::CmpRUImm32 { - op: CmpOp::CmpL64, - rn: ridx, - imm: jt_size as u32, - }); - ctx.emit(Inst::OneWayCondBr { - target: targets[0], - cond: Cond::from_intcc(IntCC::UnsignedGreaterThanOrEqual), - }); - - // Compute index scaled by entry size. - let rtmp = ctx.alloc_tmp(types::I64).only_reg().unwrap(); - ctx.emit(Inst::ShiftRR { - shift_op: ShiftOp::LShL64, - rd: rtmp, - rn: ridx, - shift_imm: 2, - shift_reg: zero_reg(), - }); - - // Emit the compound instruction that does: - // - // larl %r1, - // agf %r1, 0(%r1, %rTmp) - // br %r1 - // [jt entries] - // - // This must be *one* instruction in the vcode because - // we cannot allow regalloc to insert any spills/fills - // in the middle of the sequence; otherwise, the ADR's - // PC-rel offset to the jumptable would be incorrect. - // (The alternative is to introduce a relocation pass - // for inlined jumptables, which is much worse, IMHO.) - - ctx.emit(Inst::JTSequence { - ridx: rtmp.to_reg(), - targets: targets.to_vec(), - }); - } - - _ => panic!("Unknown branch type!"), - } - } - - Ok(()) -} - //============================================================================= // Lowering-backend trait implementation. @@ -1151,6 +417,32 @@ impl LowerBackend for S390xBackend { branches: &[IRInst], targets: &[MachLabel], ) -> CodegenResult<()> { - lower_branch(ctx, branches, targets) + // A block should end with at most two branches. The first may be a + // conditional branch; a conditional branch can be followed only by an + // unconditional branch or fallthrough. Otherwise, if only one branch, + // it may be an unconditional branch, a fallthrough, a return, or a + // trap. These conditions are verified by `is_ebb_basic()` during the + // verifier pass. + assert!(branches.len() <= 2); + if branches.len() == 2 { + let op1 = ctx.data(branches[1]).opcode(); + assert!(op1 == Opcode::Jump); + } + + // Lower the first branch in ISLE. This will automatically handle + // the second branch (if any) by emitting a two-way conditional branch. + if let Ok(()) = super::lower::isle::lower_branch( + ctx, + &self.flags, + &self.isa_flags, + branches[0], + targets, + ) { + return Ok(()); + } + unreachable!( + "implemented in ISLE: branch = `{}`", + ctx.dfg().display_inst(branches[0]), + ); } } diff --git a/cranelift/codegen/src/isa/s390x/lower/isle.rs b/cranelift/codegen/src/isa/s390x/lower/isle.rs index a40679106a..32672cf0d3 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle.rs +++ b/cranelift/codegen/src/isa/s390x/lower/isle.rs @@ -51,6 +51,28 @@ where ) } +/// The main entry point for branch lowering with ISLE. +pub(crate) fn lower_branch( + lower_ctx: &mut C, + flags: &Flags, + isa_flags: &IsaFlags, + branch: Inst, + targets: &[MachLabel], +) -> Result<(), ()> +where + C: LowerCtx, +{ + lower_common( + lower_ctx, + flags, + isa_flags, + &[], + branch, + |cx, insn| generated_code::constructor_lower_branch(cx, insn, &targets.to_vec()), + s390x_map_regs, + ) +} + impl generated_code::Context for IsleContext<'_, C, Flags, IsaFlags, 6> where C: LowerCtx, @@ -369,6 +391,16 @@ where } } + #[inline] + fn vec_length_minus1(&mut self, vec: &VecMachLabel) -> u32 { + u32::try_from(vec.len()).unwrap() - 1 + } + + #[inline] + fn vec_element(&mut self, vec: &VecMachLabel, index: u8) -> MachLabel { + vec[usize::from(index)] + } + #[inline] fn reloc_distance_near(&mut self, dist: &RelocDistance) -> Option<()> { if *dist == RelocDistance::Near { @@ -471,4 +503,9 @@ where fn emit(&mut self, inst: &MInst) -> Unit { self.emitted_insts.push((inst.clone(), false)); } + + #[inline] + fn emit_safepoint(&mut self, inst: &MInst) -> Unit { + self.emitted_insts.push((inst.clone(), true)); + } } diff --git a/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.manifest b/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.manifest index f829980d23..944b7aca45 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.manifest +++ b/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.manifest @@ -1,4 +1,4 @@ src/clif.isle 9ea75a6f790b5c03 src/prelude.isle 51d2aef2566c1c96 -src/isa/s390x/inst.isle 17b77476355c4509 -src/isa/s390x/lower.isle a0e21a567040bc33 +src/isa/s390x/inst.isle d7bfd05fb4d4a66d +src/isa/s390x/lower.isle 57dcc39cbab2d1c6 diff --git a/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs index ea1edb2ebf..3997d9c52c 100644 --- a/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/s390x/lower/isle/generated_code.rs @@ -108,6 +108,8 @@ pub trait Context { fn invert_cond(&mut self, arg0: &Cond) -> Cond; fn signed(&mut self, arg0: &IntCC) -> Option<()>; fn unsigned(&mut self, arg0: &IntCC) -> Option<()>; + fn vec_length_minus1(&mut self, arg0: &VecMachLabel) -> u32; + fn vec_element(&mut self, arg0: &VecMachLabel, arg1: u8) -> MachLabel; fn reloc_distance_near(&mut self, arg0: &RelocDistance) -> Option<()>; fn zero_offset(&mut self) -> Offset32; fn i64_from_offset(&mut self, arg0: Offset32) -> i64; @@ -122,6 +124,7 @@ pub trait Context { fn sinkable_inst(&mut self, arg0: Value) -> Option; fn sink_inst(&mut self, arg0: Inst) -> Unit; fn emit(&mut self, arg0: &MInst) -> Unit; + fn emit_safepoint(&mut self, arg0: &MInst) -> Unit; } /// Internal type SideEffectNoResult: defined at src/prelude.isle line 282. @@ -649,7 +652,7 @@ pub enum MInst { }, } -/// Internal type ALUOp: defined at src/isa/s390x/inst.isle line 689. +/// Internal type ALUOp: defined at src/isa/s390x/inst.isle line 688. #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum ALUOp { Add32, @@ -687,7 +690,7 @@ pub enum ALUOp { XorNot64, } -/// Internal type UnaryOp: defined at src/isa/s390x/inst.isle line 730. +/// Internal type UnaryOp: defined at src/isa/s390x/inst.isle line 729. #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum UnaryOp { Abs32, @@ -700,7 +703,7 @@ pub enum UnaryOp { PopcntReg, } -/// Internal type ShiftOp: defined at src/isa/s390x/inst.isle line 743. +/// Internal type ShiftOp: defined at src/isa/s390x/inst.isle line 742. #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum ShiftOp { RotL32, @@ -713,7 +716,7 @@ pub enum ShiftOp { AShR64, } -/// Internal type CmpOp: defined at src/isa/s390x/inst.isle line 756. +/// Internal type CmpOp: defined at src/isa/s390x/inst.isle line 755. #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum CmpOp { CmpS32, @@ -728,7 +731,7 @@ pub enum CmpOp { CmpL64Ext32, } -/// Internal type FPUOp1: defined at src/isa/s390x/inst.isle line 771. +/// Internal type FPUOp1: defined at src/isa/s390x/inst.isle line 770. #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum FPUOp1 { Abs32, @@ -743,7 +746,7 @@ pub enum FPUOp1 { Cvt64To32, } -/// Internal type FPUOp2: defined at src/isa/s390x/inst.isle line 786. +/// Internal type FPUOp2: defined at src/isa/s390x/inst.isle line 785. #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum FPUOp2 { Add32, @@ -760,7 +763,7 @@ pub enum FPUOp2 { Min64, } -/// Internal type FPUOp3: defined at src/isa/s390x/inst.isle line 803. +/// Internal type FPUOp3: defined at src/isa/s390x/inst.isle line 802. #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum FPUOp3 { MAdd32, @@ -769,7 +772,7 @@ pub enum FPUOp3 { MSub64, } -/// Internal type FpuToIntOp: defined at src/isa/s390x/inst.isle line 812. +/// Internal type FpuToIntOp: defined at src/isa/s390x/inst.isle line 811. #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum FpuToIntOp { F32ToU32, @@ -782,7 +785,7 @@ pub enum FpuToIntOp { F64ToI64, } -/// Internal type IntToFpuOp: defined at src/isa/s390x/inst.isle line 825. +/// Internal type IntToFpuOp: defined at src/isa/s390x/inst.isle line 824. #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum IntToFpuOp { U32ToF32, @@ -795,7 +798,7 @@ pub enum IntToFpuOp { I64ToF64, } -/// Internal type FpuRoundMode: defined at src/isa/s390x/inst.isle line 839. +/// Internal type FpuRoundMode: defined at src/isa/s390x/inst.isle line 838. #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum FpuRoundMode { Minus32, @@ -808,19 +811,19 @@ pub enum FpuRoundMode { Nearest64, } -/// Internal type WritableRegPair: defined at src/isa/s390x/inst.isle line 1236. +/// Internal type WritableRegPair: defined at src/isa/s390x/inst.isle line 1248. #[derive(Clone, Debug)] pub enum WritableRegPair { WritableRegPair { hi: WritableReg, lo: WritableReg }, } -/// Internal type RegPair: defined at src/isa/s390x/inst.isle line 1258. +/// Internal type RegPair: defined at src/isa/s390x/inst.isle line 1270. #[derive(Clone, Debug)] pub enum RegPair { RegPair { hi: Reg, lo: Reg }, } -/// Internal type ProducesBool: defined at src/isa/s390x/inst.isle line 2158. +/// Internal type ProducesBool: defined at src/isa/s390x/inst.isle line 2209. #[derive(Clone, Debug)] pub enum ProducesBool { ProducesBool { producer: ProducesFlags, cond: Cond }, @@ -960,7 +963,7 @@ pub fn constructor_mask_amt_reg(ctx: &mut C, arg0: Type, arg1: Reg) let pattern0_0 = arg0; if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) { let pattern2_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1014. + // Rule at src/isa/s390x/inst.isle line 1013. let expr0_0: i64 = -1; let expr1_0 = C::mask_amt_imm(ctx, pattern1_0, expr0_0); let expr2_0 = C::u8_as_u16(ctx, expr1_0); @@ -971,7 +974,7 @@ pub fn constructor_mask_amt_reg(ctx: &mut C, arg0: Type, arg1: Reg) } if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) { let pattern2_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1017. + // Rule at src/isa/s390x/inst.isle line 1016. return Some(pattern2_0); } return None; @@ -998,7 +1001,7 @@ pub fn constructor_lower_address( let pattern7_0 = arg2; let pattern8_0 = C::i64_from_offset(ctx, pattern7_0); if pattern8_0 == 0 { - // Rule at src/isa/s390x/inst.isle line 1100. + // Rule at src/isa/s390x/inst.isle line 1112. let expr0_0 = C::put_in_reg(ctx, pattern6_0); let expr1_0 = C::put_in_reg(ctx, pattern6_1); let expr2_0 = C::memarg_reg_plus_reg(ctx, expr0_0, expr1_0, pattern0_0); @@ -1017,7 +1020,7 @@ pub fn constructor_lower_address( if let Some(pattern8_0) = C::memarg_symbol_offset_sum(ctx, pattern6_0, pattern7_0) { - // Rule at src/isa/s390x/inst.isle line 1103. + // Rule at src/isa/s390x/inst.isle line 1115. let expr0_0 = C::memarg_symbol(ctx, pattern3_0, pattern8_0, pattern0_0); return Some(expr0_0); } @@ -1027,7 +1030,7 @@ pub fn constructor_lower_address( } let pattern2_0 = arg2; let pattern3_0 = C::i64_from_offset(ctx, pattern2_0); - // Rule at src/isa/s390x/inst.isle line 1097. + // Rule at src/isa/s390x/inst.isle line 1109. let expr0_0 = C::put_in_reg(ctx, pattern1_0); let expr1_0 = C::memarg_reg_plus_off(ctx, expr0_0, pattern3_0, pattern0_0); return Some(expr1_0); @@ -1043,7 +1046,7 @@ pub fn constructor_stack_addr_impl( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1130. + // Rule at src/isa/s390x/inst.isle line 1142. let expr0_0 = C::temp_writable_reg(ctx, pattern0_0); let expr1_0 = C::abi_stackslot_addr(ctx, expr0_0, pattern1_0, pattern2_0); let expr2_0 = C::emit(ctx, &expr1_0); @@ -1063,7 +1066,7 @@ pub fn constructor_sink_load(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C) -> Option { - // Rule at src/isa/s390x/inst.isle line 1241. + // Rule at src/isa/s390x/inst.isle line 1253. let expr0_0: u8 = 0; let expr1_0 = C::writable_gpr(ctx, expr0_0); let expr2_0: u8 = 1; @@ -1176,7 +1179,7 @@ pub fn constructor_copy_writable_regpair( arg0: &RegPair, ) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/s390x/inst.isle line 1247. + // Rule at src/isa/s390x/inst.isle line 1259. let expr0_0 = constructor_temp_writable_regpair(ctx)?; return Some(expr0_0); } @@ -1192,7 +1195,7 @@ pub fn constructor_writable_regpair_hi( lo: pattern1_1, } = pattern0_0 { - // Rule at src/isa/s390x/inst.isle line 1251. + // Rule at src/isa/s390x/inst.isle line 1263. return Some(pattern1_0); } return None; @@ -1209,7 +1212,7 @@ pub fn constructor_writable_regpair_lo( lo: pattern1_1, } = pattern0_0 { - // Rule at src/isa/s390x/inst.isle line 1255. + // Rule at src/isa/s390x/inst.isle line 1267. return Some(pattern1_1); } return None; @@ -1226,7 +1229,7 @@ pub fn constructor_writable_regpair_to_regpair( lo: pattern1_1, } = pattern0_0 { - // Rule at src/isa/s390x/inst.isle line 1262. + // Rule at src/isa/s390x/inst.isle line 1274. let expr0_0 = C::writable_reg_to_reg(ctx, pattern1_0); let expr1_0 = C::writable_reg_to_reg(ctx, pattern1_1); let expr2_0 = RegPair::RegPair { @@ -1240,7 +1243,7 @@ pub fn constructor_writable_regpair_to_regpair( // Generated as internal constructor for term uninitialized_regpair. pub fn constructor_uninitialized_regpair(ctx: &mut C) -> Option { - // Rule at src/isa/s390x/inst.isle line 1267. + // Rule at src/isa/s390x/inst.isle line 1279. let expr0_0 = constructor_temp_writable_regpair(ctx)?; let expr1_0 = constructor_writable_regpair_to_regpair(ctx, &expr0_0)?; return Some(expr1_0); @@ -1254,7 +1257,7 @@ pub fn constructor_regpair_hi(ctx: &mut C, arg0: &RegPair) -> Option lo: pattern1_1, } = pattern0_0 { - // Rule at src/isa/s390x/inst.isle line 1272. + // Rule at src/isa/s390x/inst.isle line 1284. return Some(pattern1_0); } return None; @@ -1268,7 +1271,7 @@ pub fn constructor_regpair_lo(ctx: &mut C, arg0: &RegPair) -> Option lo: pattern1_1, } = pattern0_0 { - // Rule at src/isa/s390x/inst.isle line 1276. + // Rule at src/isa/s390x/inst.isle line 1288. return Some(pattern1_1); } return None; @@ -1286,7 +1289,7 @@ pub fn constructor_alu_rrr( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 1290. + // Rule at src/isa/s390x/inst.isle line 1304. let expr0_0 = C::temp_writable_reg(ctx, pattern0_0); let expr1_0 = MInst::AluRRR { alu_op: pattern1_0.clone(), @@ -1311,7 +1314,7 @@ pub fn constructor_alu_rrsimm16( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 1297. + // Rule at src/isa/s390x/inst.isle line 1311. let expr0_0 = C::temp_writable_reg(ctx, pattern0_0); let expr1_0 = MInst::AluRRSImm16 { alu_op: pattern1_0.clone(), @@ -1336,7 +1339,7 @@ pub fn constructor_alu_rr( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 1304. + // Rule at src/isa/s390x/inst.isle line 1318. let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern2_0)?; let expr1_0 = MInst::AluRR { alu_op: pattern1_0.clone(), @@ -1360,7 +1363,7 @@ pub fn constructor_alu_rx( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 1311. + // Rule at src/isa/s390x/inst.isle line 1325. let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern2_0)?; let expr1_0 = MInst::AluRX { alu_op: pattern1_0.clone(), @@ -1384,7 +1387,7 @@ pub fn constructor_alu_rsimm16( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 1318. + // Rule at src/isa/s390x/inst.isle line 1332. let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern2_0)?; let expr1_0 = MInst::AluRSImm16 { alu_op: pattern1_0.clone(), @@ -1408,7 +1411,7 @@ pub fn constructor_alu_rsimm32( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 1325. + // Rule at src/isa/s390x/inst.isle line 1339. let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern2_0)?; let expr1_0 = MInst::AluRSImm32 { alu_op: pattern1_0.clone(), @@ -1432,7 +1435,7 @@ pub fn constructor_alu_ruimm32( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 1332. + // Rule at src/isa/s390x/inst.isle line 1346. let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern2_0)?; let expr1_0 = MInst::AluRUImm32 { alu_op: pattern1_0.clone(), @@ -1456,7 +1459,7 @@ pub fn constructor_alu_ruimm16shifted( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 1339. + // Rule at src/isa/s390x/inst.isle line 1353. let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern2_0)?; let expr1_0 = MInst::AluRUImm16Shifted { alu_op: pattern1_0.clone(), @@ -1480,7 +1483,7 @@ pub fn constructor_alu_ruimm32shifted( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 1346. + // Rule at src/isa/s390x/inst.isle line 1360. let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern2_0)?; let expr1_0 = MInst::AluRUImm32Shifted { alu_op: pattern1_0.clone(), @@ -1496,7 +1499,7 @@ pub fn constructor_alu_ruimm32shifted( pub fn constructor_smul_wide(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1353. + // Rule at src/isa/s390x/inst.isle line 1367. let expr0_0 = constructor_temp_writable_regpair(ctx)?; let expr1_0 = MInst::SMulWide { rn: pattern0_0, @@ -1511,7 +1514,7 @@ pub fn constructor_smul_wide(ctx: &mut C, arg0: Reg, arg1: Reg) -> O pub fn constructor_umul_wide(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1360. + // Rule at src/isa/s390x/inst.isle line 1374. let expr0_0 = constructor_temp_writable_regpair(ctx)?; let expr1_0 = constructor_writable_regpair_lo(ctx, &expr0_0)?; let expr2_0 = MInst::Mov64 { @@ -1533,7 +1536,7 @@ pub fn constructor_sdivmod32( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1368. + // Rule at src/isa/s390x/inst.isle line 1382. let expr0_0 = constructor_copy_writable_regpair(ctx, pattern0_0)?; let expr1_0 = MInst::SDivMod32 { rn: pattern1_0 }; let expr2_0 = C::emit(ctx, &expr1_0); @@ -1549,7 +1552,7 @@ pub fn constructor_sdivmod64( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1375. + // Rule at src/isa/s390x/inst.isle line 1389. let expr0_0 = constructor_copy_writable_regpair(ctx, pattern0_0)?; let expr1_0 = MInst::SDivMod64 { rn: pattern1_0 }; let expr2_0 = C::emit(ctx, &expr1_0); @@ -1565,7 +1568,7 @@ pub fn constructor_udivmod32( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1382. + // Rule at src/isa/s390x/inst.isle line 1396. let expr0_0 = constructor_copy_writable_regpair(ctx, pattern0_0)?; let expr1_0 = MInst::UDivMod32 { rn: pattern1_0 }; let expr2_0 = C::emit(ctx, &expr1_0); @@ -1581,7 +1584,7 @@ pub fn constructor_udivmod64( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1389. + // Rule at src/isa/s390x/inst.isle line 1403. let expr0_0 = constructor_copy_writable_regpair(ctx, pattern0_0)?; let expr1_0 = MInst::UDivMod64 { rn: pattern1_0 }; let expr2_0 = C::emit(ctx, &expr1_0); @@ -1603,7 +1606,7 @@ pub fn constructor_shift_rr( let pattern2_0 = arg2; let pattern3_0 = arg3; let pattern4_0 = arg4; - // Rule at src/isa/s390x/inst.isle line 1396. + // Rule at src/isa/s390x/inst.isle line 1410. let expr0_0 = C::temp_writable_reg(ctx, pattern0_0); let expr1_0 = MInst::ShiftRR { shift_op: pattern1_0.clone(), @@ -1627,7 +1630,7 @@ pub fn constructor_unary_rr( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1403. + // Rule at src/isa/s390x/inst.isle line 1417. let expr0_0 = C::temp_writable_reg(ctx, pattern0_0); let expr1_0 = MInst::UnaryRR { op: pattern1_0.clone(), @@ -1649,7 +1652,7 @@ pub fn constructor_cmp_rr( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1410. + // Rule at src/isa/s390x/inst.isle line 1424. let expr0_0 = MInst::CmpRR { op: pattern0_0.clone(), rn: pattern1_0, @@ -1673,7 +1676,7 @@ pub fn constructor_cmp_rx( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1416. + // Rule at src/isa/s390x/inst.isle line 1430. let expr0_0 = MInst::CmpRX { op: pattern0_0.clone(), rn: pattern1_0, @@ -1697,7 +1700,7 @@ pub fn constructor_cmp_rsimm16( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1422. + // Rule at src/isa/s390x/inst.isle line 1436. let expr0_0 = MInst::CmpRSImm16 { op: pattern0_0.clone(), rn: pattern1_0, @@ -1721,7 +1724,7 @@ pub fn constructor_cmp_rsimm32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1428. + // Rule at src/isa/s390x/inst.isle line 1442. let expr0_0 = MInst::CmpRSImm32 { op: pattern0_0.clone(), rn: pattern1_0, @@ -1745,7 +1748,7 @@ pub fn constructor_cmp_ruimm32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1434. + // Rule at src/isa/s390x/inst.isle line 1448. let expr0_0 = MInst::CmpRUImm32 { op: pattern0_0.clone(), rn: pattern1_0, @@ -1771,7 +1774,7 @@ pub fn constructor_atomic_rmw_impl( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 1440. + // Rule at src/isa/s390x/inst.isle line 1454. let expr0_0 = C::temp_writable_reg(ctx, pattern0_0); let expr1_0 = MInst::AtomicRmw { alu_op: pattern1_0.clone(), @@ -1794,7 +1797,7 @@ pub fn constructor_atomic_cas32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1447. + // Rule at src/isa/s390x/inst.isle line 1461. let expr0_0: Type = I32; let expr1_0 = constructor_copy_writable_reg(ctx, expr0_0, pattern0_0)?; let expr2_0 = MInst::AtomicCas32 { @@ -1817,7 +1820,7 @@ pub fn constructor_atomic_cas64( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1454. + // Rule at src/isa/s390x/inst.isle line 1468. let expr0_0: Type = I64; let expr1_0 = constructor_copy_writable_reg(ctx, expr0_0, pattern0_0)?; let expr2_0 = MInst::AtomicCas64 { @@ -1832,7 +1835,7 @@ pub fn constructor_atomic_cas64( // Generated as internal constructor for term fence_impl. pub fn constructor_fence_impl(ctx: &mut C) -> Option { - // Rule at src/isa/s390x/inst.isle line 1461. + // Rule at src/isa/s390x/inst.isle line 1475. let expr0_0 = MInst::Fence; let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 }; return Some(expr1_0); @@ -1841,7 +1844,7 @@ pub fn constructor_fence_impl(ctx: &mut C) -> Option(ctx: &mut C, arg0: &MemArg) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/s390x/inst.isle line 1466. + // Rule at src/isa/s390x/inst.isle line 1480. let expr0_0: Type = I32; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::Load32 { @@ -1856,7 +1859,7 @@ pub fn constructor_load32(ctx: &mut C, arg0: &MemArg) -> Option // Generated as internal constructor for term load64. pub fn constructor_load64(ctx: &mut C, arg0: &MemArg) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/s390x/inst.isle line 1473. + // Rule at src/isa/s390x/inst.isle line 1487. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::Load64 { @@ -1871,7 +1874,7 @@ pub fn constructor_load64(ctx: &mut C, arg0: &MemArg) -> Option // Generated as internal constructor for term loadrev16. pub fn constructor_loadrev16(ctx: &mut C, arg0: &MemArg) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/s390x/inst.isle line 1480. + // Rule at src/isa/s390x/inst.isle line 1494. let expr0_0: Type = I32; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::LoadRev16 { @@ -1886,7 +1889,7 @@ pub fn constructor_loadrev16(ctx: &mut C, arg0: &MemArg) -> Option(ctx: &mut C, arg0: &MemArg) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/s390x/inst.isle line 1487. + // Rule at src/isa/s390x/inst.isle line 1501. let expr0_0: Type = I32; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::LoadRev32 { @@ -1901,7 +1904,7 @@ pub fn constructor_loadrev32(ctx: &mut C, arg0: &MemArg) -> Option(ctx: &mut C, arg0: &MemArg) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/s390x/inst.isle line 1494. + // Rule at src/isa/s390x/inst.isle line 1508. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::LoadRev64 { @@ -1921,7 +1924,7 @@ pub fn constructor_store8( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1501. + // Rule at src/isa/s390x/inst.isle line 1515. let expr0_0 = MInst::Store8 { rd: pattern0_0, mem: pattern1_0.clone(), @@ -1938,7 +1941,7 @@ pub fn constructor_store16( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1506. + // Rule at src/isa/s390x/inst.isle line 1520. let expr0_0 = MInst::Store16 { rd: pattern0_0, mem: pattern1_0.clone(), @@ -1955,7 +1958,7 @@ pub fn constructor_store32( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1511. + // Rule at src/isa/s390x/inst.isle line 1525. let expr0_0 = MInst::Store32 { rd: pattern0_0, mem: pattern1_0.clone(), @@ -1972,7 +1975,7 @@ pub fn constructor_store64( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1516. + // Rule at src/isa/s390x/inst.isle line 1530. let expr0_0 = MInst::Store64 { rd: pattern0_0, mem: pattern1_0.clone(), @@ -1989,7 +1992,7 @@ pub fn constructor_store8_imm( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1521. + // Rule at src/isa/s390x/inst.isle line 1535. let expr0_0 = MInst::StoreImm8 { imm: pattern0_0, mem: pattern1_0.clone(), @@ -2006,7 +2009,7 @@ pub fn constructor_store16_imm( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1526. + // Rule at src/isa/s390x/inst.isle line 1540. let expr0_0 = MInst::StoreImm16 { imm: pattern0_0, mem: pattern1_0.clone(), @@ -2023,7 +2026,7 @@ pub fn constructor_store32_simm16( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1531. + // Rule at src/isa/s390x/inst.isle line 1545. let expr0_0 = MInst::StoreImm32SExt16 { imm: pattern0_0, mem: pattern1_0.clone(), @@ -2040,7 +2043,7 @@ pub fn constructor_store64_simm16( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1536. + // Rule at src/isa/s390x/inst.isle line 1550. let expr0_0 = MInst::StoreImm64SExt16 { imm: pattern0_0, mem: pattern1_0.clone(), @@ -2057,7 +2060,7 @@ pub fn constructor_storerev16( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1541. + // Rule at src/isa/s390x/inst.isle line 1555. let expr0_0 = MInst::StoreRev16 { rd: pattern0_0, mem: pattern1_0.clone(), @@ -2074,7 +2077,7 @@ pub fn constructor_storerev32( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1546. + // Rule at src/isa/s390x/inst.isle line 1560. let expr0_0 = MInst::StoreRev32 { rd: pattern0_0, mem: pattern1_0.clone(), @@ -2091,7 +2094,7 @@ pub fn constructor_storerev64( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1551. + // Rule at src/isa/s390x/inst.isle line 1565. let expr0_0 = MInst::StoreRev64 { rd: pattern0_0, mem: pattern1_0.clone(), @@ -2110,7 +2113,7 @@ pub fn constructor_fpu_rr( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1556. + // Rule at src/isa/s390x/inst.isle line 1570. let expr0_0 = C::temp_writable_reg(ctx, pattern0_0); let expr1_0 = MInst::FpuRR { fpu_op: pattern1_0.clone(), @@ -2134,7 +2137,7 @@ pub fn constructor_fpu_rrr( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 1563. + // Rule at src/isa/s390x/inst.isle line 1577. let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern2_0)?; let expr1_0 = MInst::FpuRRR { fpu_op: pattern1_0.clone(), @@ -2160,7 +2163,7 @@ pub fn constructor_fpu_rrrr( let pattern2_0 = arg2; let pattern3_0 = arg3; let pattern4_0 = arg4; - // Rule at src/isa/s390x/inst.isle line 1570. + // Rule at src/isa/s390x/inst.isle line 1584. let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern2_0)?; let expr1_0 = MInst::FpuRRRR { fpu_op: pattern1_0.clone(), @@ -2183,7 +2186,7 @@ pub fn constructor_fpu_copysign( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1577. + // Rule at src/isa/s390x/inst.isle line 1591. let expr0_0 = C::temp_writable_reg(ctx, pattern0_0); let expr1_0 = MInst::FpuCopysign { rd: expr0_0, @@ -2203,7 +2206,7 @@ pub fn constructor_fpu_cmp32( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1584. + // Rule at src/isa/s390x/inst.isle line 1598. let expr0_0 = MInst::FpuCmp32 { rn: pattern0_0, rm: pattern1_0, @@ -2224,7 +2227,7 @@ pub fn constructor_fpu_cmp64( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1590. + // Rule at src/isa/s390x/inst.isle line 1604. let expr0_0 = MInst::FpuCmp64 { rn: pattern0_0, rm: pattern1_0, @@ -2247,7 +2250,7 @@ pub fn constructor_fpu_to_int( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1596. + // Rule at src/isa/s390x/inst.isle line 1610. let expr0_0 = C::temp_writable_reg(ctx, pattern0_0); let expr1_0 = MInst::FpuToInt { op: pattern1_0.clone(), @@ -2272,7 +2275,7 @@ pub fn constructor_int_to_fpu( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1603. + // Rule at src/isa/s390x/inst.isle line 1617. let expr0_0 = C::temp_writable_reg(ctx, pattern0_0); let expr1_0 = MInst::IntToFpu { op: pattern1_0.clone(), @@ -2294,7 +2297,7 @@ pub fn constructor_fpu_round( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1610. + // Rule at src/isa/s390x/inst.isle line 1624. let expr0_0 = C::temp_writable_reg(ctx, pattern0_0); let expr1_0 = MInst::FpuRound { op: pattern1_0.clone(), @@ -2318,7 +2321,7 @@ pub fn constructor_fpuvec_rrr( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 1617. + // Rule at src/isa/s390x/inst.isle line 1631. let expr0_0 = C::temp_writable_reg(ctx, pattern0_0); let expr1_0 = MInst::FpuVecRRR { fpu_op: pattern1_0.clone(), @@ -2334,7 +2337,7 @@ pub fn constructor_fpuvec_rrr( // Generated as internal constructor for term mov_to_fpr. pub fn constructor_mov_to_fpr(ctx: &mut C, arg0: Reg) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/s390x/inst.isle line 1624. + // Rule at src/isa/s390x/inst.isle line 1638. let expr0_0: Type = F64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::MovToFpr { @@ -2349,7 +2352,7 @@ pub fn constructor_mov_to_fpr(ctx: &mut C, arg0: Reg) -> Option // Generated as internal constructor for term mov_from_fpr. pub fn constructor_mov_from_fpr(ctx: &mut C, arg0: Reg) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/s390x/inst.isle line 1631. + // Rule at src/isa/s390x/inst.isle line 1645. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::MovFromFpr { @@ -2364,7 +2367,7 @@ pub fn constructor_mov_from_fpr(ctx: &mut C, arg0: Reg) -> Option(ctx: &mut C, arg0: &MemArg) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/s390x/inst.isle line 1638. + // Rule at src/isa/s390x/inst.isle line 1652. let expr0_0: Type = F32; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::FpuLoad32 { @@ -2379,7 +2382,7 @@ pub fn constructor_fpu_load32(ctx: &mut C, arg0: &MemArg) -> Option< // Generated as internal constructor for term fpu_load64. pub fn constructor_fpu_load64(ctx: &mut C, arg0: &MemArg) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/s390x/inst.isle line 1645. + // Rule at src/isa/s390x/inst.isle line 1659. let expr0_0: Type = F64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::FpuLoad64 { @@ -2394,7 +2397,7 @@ pub fn constructor_fpu_load64(ctx: &mut C, arg0: &MemArg) -> Option< // Generated as internal constructor for term fpu_loadrev32. pub fn constructor_fpu_loadrev32(ctx: &mut C, arg0: &MemArg) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/s390x/inst.isle line 1652. + // Rule at src/isa/s390x/inst.isle line 1666. let expr0_0: Type = F32; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::FpuLoadRev32 { @@ -2409,7 +2412,7 @@ pub fn constructor_fpu_loadrev32(ctx: &mut C, arg0: &MemArg) -> Opti // Generated as internal constructor for term fpu_loadrev64. pub fn constructor_fpu_loadrev64(ctx: &mut C, arg0: &MemArg) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/s390x/inst.isle line 1659. + // Rule at src/isa/s390x/inst.isle line 1673. let expr0_0: Type = F64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::FpuLoadRev64 { @@ -2429,7 +2432,7 @@ pub fn constructor_fpu_store32( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1666. + // Rule at src/isa/s390x/inst.isle line 1680. let expr0_0 = MInst::FpuStore32 { rd: pattern0_0, mem: pattern1_0.clone(), @@ -2446,7 +2449,7 @@ pub fn constructor_fpu_store64( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1671. + // Rule at src/isa/s390x/inst.isle line 1685. let expr0_0 = MInst::FpuStore64 { rd: pattern0_0, mem: pattern1_0.clone(), @@ -2463,7 +2466,7 @@ pub fn constructor_fpu_storerev32( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1676. + // Rule at src/isa/s390x/inst.isle line 1690. let expr0_0 = MInst::FpuStoreRev32 { rd: pattern0_0, mem: pattern1_0.clone(), @@ -2480,7 +2483,7 @@ pub fn constructor_fpu_storerev64( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1681. + // Rule at src/isa/s390x/inst.isle line 1695. let expr0_0 = MInst::FpuStoreRev64 { rd: pattern0_0, mem: pattern1_0.clone(), @@ -2497,7 +2500,7 @@ pub fn constructor_load_ext_name_far( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1686. + // Rule at src/isa/s390x/inst.isle line 1700. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::LoadExtNameFar { @@ -2513,7 +2516,7 @@ pub fn constructor_load_ext_name_far( // Generated as internal constructor for term load_addr. pub fn constructor_load_addr(ctx: &mut C, arg0: &MemArg) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/s390x/inst.isle line 1693. + // Rule at src/isa/s390x/inst.isle line 1707. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::LoadAddr { @@ -2525,6 +2528,72 @@ pub fn constructor_load_addr(ctx: &mut C, arg0: &MemArg) -> Option( + ctx: &mut C, + arg0: MachLabel, +) -> Option { + let pattern0_0 = arg0; + // Rule at src/isa/s390x/inst.isle line 1714. + let expr0_0 = MInst::Jump { dest: pattern0_0 }; + let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 }; + return Some(expr1_0); +} + +// Generated as internal constructor for term cond_br. +pub fn constructor_cond_br( + ctx: &mut C, + arg0: MachLabel, + arg1: MachLabel, + arg2: &Cond, +) -> Option { + let pattern0_0 = arg0; + let pattern1_0 = arg1; + let pattern2_0 = arg2; + // Rule at src/isa/s390x/inst.isle line 1719. + let expr0_0 = MInst::CondBr { + taken: pattern0_0, + not_taken: pattern1_0, + cond: pattern2_0.clone(), + }; + let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 }; + return Some(expr1_0); +} + +// Generated as internal constructor for term oneway_cond_br. +pub fn constructor_oneway_cond_br( + ctx: &mut C, + arg0: MachLabel, + arg1: &Cond, +) -> Option { + let pattern0_0 = arg0; + let pattern1_0 = arg1; + // Rule at src/isa/s390x/inst.isle line 1724. + let expr0_0 = MInst::OneWayCondBr { + target: pattern0_0, + cond: pattern1_0.clone(), + }; + let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 }; + return Some(expr1_0); +} + +// Generated as internal constructor for term jt_sequence. +pub fn constructor_jt_sequence( + ctx: &mut C, + arg0: Reg, + arg1: &VecMachLabel, +) -> Option { + let pattern0_0 = arg0; + let pattern1_0 = arg1; + // Rule at src/isa/s390x/inst.isle line 1729. + let expr0_0 = MInst::JTSequence { + ridx: pattern0_0, + targets: pattern1_0.clone(), + }; + let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 }; + return Some(expr1_0); +} + // Generated as internal constructor for term drop_flags. pub fn constructor_drop_flags(ctx: &mut C, arg0: &ProducesFlags) -> Option { let pattern0_0 = arg0; @@ -2533,7 +2602,7 @@ pub fn constructor_drop_flags(ctx: &mut C, arg0: &ProducesFlags) -> result: pattern1_1, } = pattern0_0 { - // Rule at src/isa/s390x/inst.isle line 1700. + // Rule at src/isa/s390x/inst.isle line 1734. let expr0_0 = C::emit(ctx, &pattern1_0); return Some(pattern1_1); } @@ -2551,7 +2620,7 @@ pub fn constructor_emit_mov( if pattern0_0 == F32 { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1716. + // Rule at src/isa/s390x/inst.isle line 1750. let expr0_0 = MInst::FpuMove32 { rd: pattern2_0, rn: pattern3_0, @@ -2562,7 +2631,7 @@ pub fn constructor_emit_mov( if pattern0_0 == F64 { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1719. + // Rule at src/isa/s390x/inst.isle line 1753. let expr0_0 = MInst::FpuMove64 { rd: pattern2_0, rn: pattern3_0, @@ -2573,7 +2642,7 @@ pub fn constructor_emit_mov( if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1710. + // Rule at src/isa/s390x/inst.isle line 1744. let expr0_0 = MInst::Mov32 { rd: pattern2_0, rm: pattern3_0, @@ -2584,7 +2653,7 @@ pub fn constructor_emit_mov( if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1713. + // Rule at src/isa/s390x/inst.isle line 1747. let expr0_0 = MInst::Mov64 { rd: pattern2_0, rm: pattern3_0, @@ -2603,7 +2672,7 @@ pub fn constructor_copy_writable_reg( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1724. + // Rule at src/isa/s390x/inst.isle line 1758. let expr0_0 = C::temp_writable_reg(ctx, pattern0_0); let expr1_0 = constructor_emit_mov(ctx, pattern0_0, expr0_0, pattern1_0)?; return Some(expr0_0); @@ -2613,7 +2682,7 @@ pub fn constructor_copy_writable_reg( pub fn constructor_copy_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1731. + // Rule at src/isa/s390x/inst.isle line 1765. let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern1_0)?; let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0); return Some(expr1_0); @@ -2630,7 +2699,7 @@ pub fn constructor_emit_imm( if pattern0_0 == F32 { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1786. + // Rule at src/isa/s390x/inst.isle line 1820. let expr0_0 = C::u64_as_u32(ctx, pattern3_0); let expr1_0 = MInst::LoadFpuConst32 { rd: pattern2_0, @@ -2642,7 +2711,7 @@ pub fn constructor_emit_imm( if pattern0_0 == F64 { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1791. + // Rule at src/isa/s390x/inst.isle line 1825. let expr0_0 = MInst::LoadFpuConst64 { rd: pattern2_0, const_data: pattern3_0, @@ -2653,7 +2722,7 @@ pub fn constructor_emit_imm( if let Some(pattern1_0) = C::fits_in_16(ctx, pattern0_0) { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1740. + // Rule at src/isa/s390x/inst.isle line 1774. let expr0_0 = C::u64_as_i16(ctx, pattern3_0); let expr1_0 = MInst::Mov32SImm16 { rd: pattern2_0, @@ -2666,7 +2735,7 @@ pub fn constructor_emit_imm( let pattern2_0 = arg1; let pattern3_0 = arg2; if let Some(pattern4_0) = C::i16_from_u64(ctx, pattern3_0) { - // Rule at src/isa/s390x/inst.isle line 1744. + // Rule at src/isa/s390x/inst.isle line 1778. let expr0_0 = MInst::Mov32SImm16 { rd: pattern2_0, imm: pattern4_0, @@ -2674,7 +2743,7 @@ pub fn constructor_emit_imm( let expr1_0 = C::emit(ctx, &expr0_0); return Some(expr1_0); } - // Rule at src/isa/s390x/inst.isle line 1748. + // Rule at src/isa/s390x/inst.isle line 1782. let expr0_0 = C::u64_as_u32(ctx, pattern3_0); let expr1_0 = MInst::Mov32Imm { rd: pattern2_0, @@ -2688,14 +2757,14 @@ pub fn constructor_emit_imm( let pattern3_0 = arg2; if let Some(pattern4_0) = C::u64_nonzero_hipart(ctx, pattern3_0) { if let Some(pattern5_0) = C::u64_nonzero_lopart(ctx, pattern3_0) { - // Rule at src/isa/s390x/inst.isle line 1768. + // Rule at src/isa/s390x/inst.isle line 1802. let expr0_0 = constructor_emit_imm(ctx, pattern1_0, pattern2_0, pattern4_0)?; let expr1_0 = constructor_emit_insert_imm(ctx, pattern2_0, pattern5_0)?; return Some(expr1_0); } } if let Some(pattern4_0) = C::i16_from_u64(ctx, pattern3_0) { - // Rule at src/isa/s390x/inst.isle line 1752. + // Rule at src/isa/s390x/inst.isle line 1786. let expr0_0 = MInst::Mov64SImm16 { rd: pattern2_0, imm: pattern4_0, @@ -2704,7 +2773,7 @@ pub fn constructor_emit_imm( return Some(expr1_0); } if let Some(pattern4_0) = C::i32_from_u64(ctx, pattern3_0) { - // Rule at src/isa/s390x/inst.isle line 1756. + // Rule at src/isa/s390x/inst.isle line 1790. let expr0_0 = MInst::Mov64SImm32 { rd: pattern2_0, imm: pattern4_0, @@ -2713,7 +2782,7 @@ pub fn constructor_emit_imm( return Some(expr1_0); } if let Some(pattern4_0) = C::uimm32shifted_from_u64(ctx, pattern3_0) { - // Rule at src/isa/s390x/inst.isle line 1764. + // Rule at src/isa/s390x/inst.isle line 1798. let expr0_0 = MInst::Mov64UImm32Shifted { rd: pattern2_0, imm: pattern4_0, @@ -2722,7 +2791,7 @@ pub fn constructor_emit_imm( return Some(expr1_0); } if let Some(pattern4_0) = C::uimm16shifted_from_u64(ctx, pattern3_0) { - // Rule at src/isa/s390x/inst.isle line 1760. + // Rule at src/isa/s390x/inst.isle line 1794. let expr0_0 = MInst::Mov64UImm16Shifted { rd: pattern2_0, imm: pattern4_0, @@ -2743,7 +2812,7 @@ pub fn constructor_emit_insert_imm( let pattern0_0 = arg0; let pattern1_0 = arg1; if let Some(pattern2_0) = C::uimm32shifted_from_u64(ctx, pattern1_0) { - // Rule at src/isa/s390x/inst.isle line 1781. + // Rule at src/isa/s390x/inst.isle line 1815. let expr0_0 = MInst::Insert64UImm32Shifted { rd: pattern0_0, imm: pattern2_0, @@ -2752,7 +2821,7 @@ pub fn constructor_emit_insert_imm( return Some(expr1_0); } if let Some(pattern2_0) = C::uimm16shifted_from_u64(ctx, pattern1_0) { - // Rule at src/isa/s390x/inst.isle line 1777. + // Rule at src/isa/s390x/inst.isle line 1811. let expr0_0 = MInst::Insert64UImm16Shifted { rd: pattern0_0, imm: pattern2_0, @@ -2767,7 +2836,7 @@ pub fn constructor_emit_insert_imm( pub fn constructor_imm(ctx: &mut C, arg0: Type, arg1: u64) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1796. + // Rule at src/isa/s390x/inst.isle line 1830. let expr0_0 = C::temp_writable_reg(ctx, pattern0_0); let expr1_0 = constructor_emit_imm(ctx, pattern0_0, expr0_0, pattern1_0)?; let expr2_0 = C::writable_reg_to_reg(ctx, expr0_0); @@ -2784,7 +2853,7 @@ pub fn constructor_imm_regpair_lo( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1804. + // Rule at src/isa/s390x/inst.isle line 1838. let expr0_0 = constructor_copy_writable_regpair(ctx, pattern2_0)?; let expr1_0 = constructor_writable_regpair_lo(ctx, &expr0_0)?; let expr2_0 = constructor_emit_imm(ctx, pattern0_0, expr1_0, pattern1_0)?; @@ -2802,7 +2871,7 @@ pub fn constructor_imm_regpair_hi( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1812. + // Rule at src/isa/s390x/inst.isle line 1846. let expr0_0 = constructor_copy_writable_regpair(ctx, pattern2_0)?; let expr1_0 = constructor_writable_regpair_hi(ctx, &expr0_0)?; let expr2_0 = constructor_emit_imm(ctx, pattern0_0, expr1_0, pattern1_0)?; @@ -2814,22 +2883,22 @@ pub fn constructor_imm_regpair_hi( pub fn constructor_ty_ext32(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I8 { - // Rule at src/isa/s390x/inst.isle line 1822. + // Rule at src/isa/s390x/inst.isle line 1856. let expr0_0: Type = I32; return Some(expr0_0); } if pattern0_0 == I16 { - // Rule at src/isa/s390x/inst.isle line 1823. + // Rule at src/isa/s390x/inst.isle line 1857. let expr0_0: Type = I32; return Some(expr0_0); } if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 1824. + // Rule at src/isa/s390x/inst.isle line 1858. let expr0_0: Type = I32; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 1825. + // Rule at src/isa/s390x/inst.isle line 1859. let expr0_0: Type = I64; return Some(expr0_0); } @@ -2840,22 +2909,22 @@ pub fn constructor_ty_ext32(ctx: &mut C, arg0: Type) -> Option pub fn constructor_ty_ext64(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I8 { - // Rule at src/isa/s390x/inst.isle line 1829. + // Rule at src/isa/s390x/inst.isle line 1863. let expr0_0: Type = I64; return Some(expr0_0); } if pattern0_0 == I16 { - // Rule at src/isa/s390x/inst.isle line 1830. + // Rule at src/isa/s390x/inst.isle line 1864. let expr0_0: Type = I64; return Some(expr0_0); } if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 1831. + // Rule at src/isa/s390x/inst.isle line 1865. let expr0_0: Type = I64; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 1832. + // Rule at src/isa/s390x/inst.isle line 1866. let expr0_0: Type = I64; return Some(expr0_0); } @@ -2872,7 +2941,7 @@ pub fn constructor_emit_zext32_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1837. + // Rule at src/isa/s390x/inst.isle line 1871. let expr0_0: bool = false; let expr1_0 = C::ty_bits(ctx, pattern1_0); let expr2_0: u8 = 32; @@ -2897,7 +2966,7 @@ pub fn constructor_emit_sext32_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1843. + // Rule at src/isa/s390x/inst.isle line 1877. let expr0_0: bool = true; let expr1_0 = C::ty_bits(ctx, pattern1_0); let expr2_0: u8 = 32; @@ -2922,7 +2991,7 @@ pub fn constructor_emit_zext64_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1849. + // Rule at src/isa/s390x/inst.isle line 1883. let expr0_0: bool = false; let expr1_0 = C::ty_bits(ctx, pattern1_0); let expr2_0: u8 = 64; @@ -2947,7 +3016,7 @@ pub fn constructor_emit_sext64_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1855. + // Rule at src/isa/s390x/inst.isle line 1889. let expr0_0: bool = true; let expr1_0 = C::ty_bits(ctx, pattern1_0); let expr2_0: u8 = 64; @@ -2966,7 +3035,7 @@ pub fn constructor_emit_sext64_reg( pub fn constructor_zext32_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1861. + // Rule at src/isa/s390x/inst.isle line 1895. let expr0_0: Type = I32; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = constructor_emit_zext32_reg(ctx, expr1_0, pattern0_0, pattern1_0)?; @@ -2978,7 +3047,7 @@ pub fn constructor_zext32_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> pub fn constructor_sext32_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1869. + // Rule at src/isa/s390x/inst.isle line 1903. let expr0_0: Type = I32; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = constructor_emit_sext32_reg(ctx, expr1_0, pattern0_0, pattern1_0)?; @@ -2990,7 +3059,7 @@ pub fn constructor_sext32_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> pub fn constructor_zext64_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1877. + // Rule at src/isa/s390x/inst.isle line 1911. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = constructor_emit_zext64_reg(ctx, expr1_0, pattern0_0, pattern1_0)?; @@ -3002,7 +3071,7 @@ pub fn constructor_zext64_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> pub fn constructor_sext64_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1885. + // Rule at src/isa/s390x/inst.isle line 1919. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = constructor_emit_sext64_reg(ctx, expr1_0, pattern0_0, pattern1_0)?; @@ -3021,7 +3090,7 @@ pub fn constructor_emit_zext32_mem( let pattern1_0 = arg1; if pattern1_0 == I8 { let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1893. + // Rule at src/isa/s390x/inst.isle line 1927. let expr0_0 = MInst::Load32ZExt8 { rd: pattern0_0, mem: pattern3_0.clone(), @@ -3031,7 +3100,7 @@ pub fn constructor_emit_zext32_mem( } if pattern1_0 == I16 { let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1894. + // Rule at src/isa/s390x/inst.isle line 1928. let expr0_0 = MInst::Load32ZExt16 { rd: pattern0_0, mem: pattern3_0.clone(), @@ -3053,7 +3122,7 @@ pub fn constructor_emit_sext32_mem( let pattern1_0 = arg1; if pattern1_0 == I8 { let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1898. + // Rule at src/isa/s390x/inst.isle line 1932. let expr0_0 = MInst::Load32SExt8 { rd: pattern0_0, mem: pattern3_0.clone(), @@ -3063,7 +3132,7 @@ pub fn constructor_emit_sext32_mem( } if pattern1_0 == I16 { let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1899. + // Rule at src/isa/s390x/inst.isle line 1933. let expr0_0 = MInst::Load32SExt16 { rd: pattern0_0, mem: pattern3_0.clone(), @@ -3085,7 +3154,7 @@ pub fn constructor_emit_zext64_mem( let pattern1_0 = arg1; if pattern1_0 == I8 { let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1903. + // Rule at src/isa/s390x/inst.isle line 1937. let expr0_0 = MInst::Load64ZExt8 { rd: pattern0_0, mem: pattern3_0.clone(), @@ -3095,7 +3164,7 @@ pub fn constructor_emit_zext64_mem( } if pattern1_0 == I16 { let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1904. + // Rule at src/isa/s390x/inst.isle line 1938. let expr0_0 = MInst::Load64ZExt16 { rd: pattern0_0, mem: pattern3_0.clone(), @@ -3105,7 +3174,7 @@ pub fn constructor_emit_zext64_mem( } if pattern1_0 == I32 { let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1905. + // Rule at src/isa/s390x/inst.isle line 1939. let expr0_0 = MInst::Load64ZExt32 { rd: pattern0_0, mem: pattern3_0.clone(), @@ -3127,7 +3196,7 @@ pub fn constructor_emit_sext64_mem( let pattern1_0 = arg1; if pattern1_0 == I8 { let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1909. + // Rule at src/isa/s390x/inst.isle line 1943. let expr0_0 = MInst::Load64SExt8 { rd: pattern0_0, mem: pattern3_0.clone(), @@ -3137,7 +3206,7 @@ pub fn constructor_emit_sext64_mem( } if pattern1_0 == I16 { let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1910. + // Rule at src/isa/s390x/inst.isle line 1944. let expr0_0 = MInst::Load64SExt16 { rd: pattern0_0, mem: pattern3_0.clone(), @@ -3147,7 +3216,7 @@ pub fn constructor_emit_sext64_mem( } if pattern1_0 == I32 { let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 1911. + // Rule at src/isa/s390x/inst.isle line 1945. let expr0_0 = MInst::Load64SExt32 { rd: pattern0_0, mem: pattern3_0.clone(), @@ -3162,7 +3231,7 @@ pub fn constructor_emit_sext64_mem( pub fn constructor_zext32_mem(ctx: &mut C, arg0: Type, arg1: &MemArg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1915. + // Rule at src/isa/s390x/inst.isle line 1949. let expr0_0: Type = I32; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = constructor_emit_zext32_mem(ctx, expr1_0, pattern0_0, pattern1_0)?; @@ -3174,7 +3243,7 @@ pub fn constructor_zext32_mem(ctx: &mut C, arg0: Type, arg1: &MemArg pub fn constructor_sext32_mem(ctx: &mut C, arg0: Type, arg1: &MemArg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1922. + // Rule at src/isa/s390x/inst.isle line 1956. let expr0_0: Type = I32; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = constructor_emit_sext32_mem(ctx, expr1_0, pattern0_0, pattern1_0)?; @@ -3186,7 +3255,7 @@ pub fn constructor_sext32_mem(ctx: &mut C, arg0: Type, arg1: &MemArg pub fn constructor_zext64_mem(ctx: &mut C, arg0: Type, arg1: &MemArg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1929. + // Rule at src/isa/s390x/inst.isle line 1963. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = constructor_emit_zext64_mem(ctx, expr1_0, pattern0_0, pattern1_0)?; @@ -3198,7 +3267,7 @@ pub fn constructor_zext64_mem(ctx: &mut C, arg0: Type, arg1: &MemArg pub fn constructor_sext64_mem(ctx: &mut C, arg0: Type, arg1: &MemArg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 1936. + // Rule at src/isa/s390x/inst.isle line 1970. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = constructor_emit_sext64_mem(ctx, expr1_0, pattern0_0, pattern1_0)?; @@ -3216,7 +3285,7 @@ pub fn constructor_emit_put_in_reg_zext32( let pattern1_0 = arg1; let pattern2_0 = C::value_type(ctx, pattern1_0); if let Some(pattern3_0) = C::u64_from_value(ctx, pattern1_0) { - // Rule at src/isa/s390x/inst.isle line 1944. + // Rule at src/isa/s390x/inst.isle line 1978. let expr0_0 = constructor_ty_ext32(ctx, pattern2_0)?; let expr1_0 = constructor_emit_imm(ctx, expr0_0, pattern0_0, pattern3_0)?; return Some(expr1_0); @@ -3233,7 +3302,7 @@ pub fn constructor_emit_put_in_reg_zext32( { if let &Opcode::Load = &pattern6_0 { if let Some(()) = C::bigendian(ctx, pattern6_2) { - // Rule at src/isa/s390x/inst.isle line 1946. + // Rule at src/isa/s390x/inst.isle line 1980. let expr0_0 = constructor_sink_load(ctx, pattern4_0)?; let expr1_0 = constructor_emit_zext32_mem(ctx, pattern0_0, pattern3_0, &expr0_0)?; @@ -3242,13 +3311,13 @@ pub fn constructor_emit_put_in_reg_zext32( } } } - // Rule at src/isa/s390x/inst.isle line 1948. + // Rule at src/isa/s390x/inst.isle line 1982. let expr0_0 = C::put_in_reg(ctx, pattern1_0); let expr1_0 = constructor_emit_zext32_reg(ctx, pattern0_0, pattern3_0, expr0_0)?; return Some(expr1_0); } if let Some(pattern3_0) = C::ty_32_or_64(ctx, pattern2_0) { - // Rule at src/isa/s390x/inst.isle line 1950. + // Rule at src/isa/s390x/inst.isle line 1984. let expr0_0 = C::put_in_reg(ctx, pattern1_0); let expr1_0 = constructor_emit_mov(ctx, pattern3_0, pattern0_0, expr0_0)?; return Some(expr1_0); @@ -3266,7 +3335,7 @@ pub fn constructor_emit_put_in_reg_sext32( let pattern1_0 = arg1; let pattern2_0 = C::value_type(ctx, pattern1_0); if let Some(pattern3_0) = C::u64_from_signed_value(ctx, pattern1_0) { - // Rule at src/isa/s390x/inst.isle line 1955. + // Rule at src/isa/s390x/inst.isle line 1989. let expr0_0 = constructor_ty_ext32(ctx, pattern2_0)?; let expr1_0 = constructor_emit_imm(ctx, expr0_0, pattern0_0, pattern3_0)?; return Some(expr1_0); @@ -3283,7 +3352,7 @@ pub fn constructor_emit_put_in_reg_sext32( { if let &Opcode::Load = &pattern6_0 { if let Some(()) = C::bigendian(ctx, pattern6_2) { - // Rule at src/isa/s390x/inst.isle line 1957. + // Rule at src/isa/s390x/inst.isle line 1991. let expr0_0 = constructor_sink_load(ctx, pattern4_0)?; let expr1_0 = constructor_emit_sext32_mem(ctx, pattern0_0, pattern3_0, &expr0_0)?; @@ -3292,13 +3361,13 @@ pub fn constructor_emit_put_in_reg_sext32( } } } - // Rule at src/isa/s390x/inst.isle line 1959. + // Rule at src/isa/s390x/inst.isle line 1993. let expr0_0 = C::put_in_reg(ctx, pattern1_0); let expr1_0 = constructor_emit_sext32_reg(ctx, pattern0_0, pattern3_0, expr0_0)?; return Some(expr1_0); } if let Some(pattern3_0) = C::ty_32_or_64(ctx, pattern2_0) { - // Rule at src/isa/s390x/inst.isle line 1961. + // Rule at src/isa/s390x/inst.isle line 1995. let expr0_0 = C::put_in_reg(ctx, pattern1_0); let expr1_0 = constructor_emit_mov(ctx, pattern3_0, pattern0_0, expr0_0)?; return Some(expr1_0); @@ -3316,7 +3385,7 @@ pub fn constructor_emit_put_in_reg_zext64( let pattern1_0 = arg1; let pattern2_0 = C::value_type(ctx, pattern1_0); if let Some(pattern3_0) = C::u64_from_value(ctx, pattern1_0) { - // Rule at src/isa/s390x/inst.isle line 1966. + // Rule at src/isa/s390x/inst.isle line 2000. let expr0_0 = constructor_ty_ext64(ctx, pattern2_0)?; let expr1_0 = constructor_emit_imm(ctx, expr0_0, pattern0_0, pattern3_0)?; return Some(expr1_0); @@ -3333,7 +3402,7 @@ pub fn constructor_emit_put_in_reg_zext64( { if let &Opcode::Load = &pattern6_0 { if let Some(()) = C::bigendian(ctx, pattern6_2) { - // Rule at src/isa/s390x/inst.isle line 1968. + // Rule at src/isa/s390x/inst.isle line 2002. let expr0_0 = constructor_sink_load(ctx, pattern4_0)?; let expr1_0 = constructor_emit_zext64_mem(ctx, pattern0_0, pattern3_0, &expr0_0)?; @@ -3342,13 +3411,13 @@ pub fn constructor_emit_put_in_reg_zext64( } } } - // Rule at src/isa/s390x/inst.isle line 1970. + // Rule at src/isa/s390x/inst.isle line 2004. let expr0_0 = C::put_in_reg(ctx, pattern1_0); let expr1_0 = constructor_emit_zext64_reg(ctx, pattern0_0, pattern3_0, expr0_0)?; return Some(expr1_0); } if let Some(pattern3_0) = C::gpr64_ty(ctx, pattern2_0) { - // Rule at src/isa/s390x/inst.isle line 1972. + // Rule at src/isa/s390x/inst.isle line 2006. let expr0_0 = C::put_in_reg(ctx, pattern1_0); let expr1_0 = constructor_emit_mov(ctx, pattern3_0, pattern0_0, expr0_0)?; return Some(expr1_0); @@ -3366,7 +3435,7 @@ pub fn constructor_emit_put_in_reg_sext64( let pattern1_0 = arg1; let pattern2_0 = C::value_type(ctx, pattern1_0); if let Some(pattern3_0) = C::u64_from_signed_value(ctx, pattern1_0) { - // Rule at src/isa/s390x/inst.isle line 1977. + // Rule at src/isa/s390x/inst.isle line 2011. let expr0_0 = constructor_ty_ext64(ctx, pattern2_0)?; let expr1_0 = constructor_emit_imm(ctx, expr0_0, pattern0_0, pattern3_0)?; return Some(expr1_0); @@ -3383,7 +3452,7 @@ pub fn constructor_emit_put_in_reg_sext64( { if let &Opcode::Load = &pattern6_0 { if let Some(()) = C::bigendian(ctx, pattern6_2) { - // Rule at src/isa/s390x/inst.isle line 1979. + // Rule at src/isa/s390x/inst.isle line 2013. let expr0_0 = constructor_sink_load(ctx, pattern4_0)?; let expr1_0 = constructor_emit_sext64_mem(ctx, pattern0_0, pattern3_0, &expr0_0)?; @@ -3392,13 +3461,13 @@ pub fn constructor_emit_put_in_reg_sext64( } } } - // Rule at src/isa/s390x/inst.isle line 1981. + // Rule at src/isa/s390x/inst.isle line 2015. let expr0_0 = C::put_in_reg(ctx, pattern1_0); let expr1_0 = constructor_emit_sext64_reg(ctx, pattern0_0, pattern3_0, expr0_0)?; return Some(expr1_0); } if let Some(pattern3_0) = C::gpr64_ty(ctx, pattern2_0) { - // Rule at src/isa/s390x/inst.isle line 1983. + // Rule at src/isa/s390x/inst.isle line 2017. let expr0_0 = C::put_in_reg(ctx, pattern1_0); let expr1_0 = constructor_emit_mov(ctx, pattern3_0, pattern0_0, expr0_0)?; return Some(expr1_0); @@ -3411,7 +3480,7 @@ pub fn constructor_put_in_reg_zext32(ctx: &mut C, arg0: Value) -> Op let pattern0_0 = arg0; let pattern1_0 = C::value_type(ctx, pattern0_0); if let Some(pattern2_0) = C::u64_from_value(ctx, pattern0_0) { - // Rule at src/isa/s390x/inst.isle line 1988. + // Rule at src/isa/s390x/inst.isle line 2022. let expr0_0 = constructor_ty_ext32(ctx, pattern1_0)?; let expr1_0 = constructor_imm(ctx, expr0_0, pattern2_0)?; return Some(expr1_0); @@ -3428,7 +3497,7 @@ pub fn constructor_put_in_reg_zext32(ctx: &mut C, arg0: Value) -> Op { if let &Opcode::Load = &pattern5_0 { if let Some(()) = C::bigendian(ctx, pattern5_2) { - // Rule at src/isa/s390x/inst.isle line 1990. + // Rule at src/isa/s390x/inst.isle line 2024. let expr0_0 = constructor_sink_load(ctx, pattern3_0)?; let expr1_0 = constructor_zext32_mem(ctx, pattern2_0, &expr0_0)?; return Some(expr1_0); @@ -3436,13 +3505,13 @@ pub fn constructor_put_in_reg_zext32(ctx: &mut C, arg0: Value) -> Op } } } - // Rule at src/isa/s390x/inst.isle line 1992. + // Rule at src/isa/s390x/inst.isle line 2026. let expr0_0 = C::put_in_reg(ctx, pattern0_0); let expr1_0 = constructor_zext32_reg(ctx, pattern2_0, expr0_0)?; return Some(expr1_0); } if let Some(pattern2_0) = C::ty_32_or_64(ctx, pattern1_0) { - // Rule at src/isa/s390x/inst.isle line 1994. + // Rule at src/isa/s390x/inst.isle line 2028. let expr0_0 = C::put_in_reg(ctx, pattern0_0); return Some(expr0_0); } @@ -3454,7 +3523,7 @@ pub fn constructor_put_in_reg_sext32(ctx: &mut C, arg0: Value) -> Op let pattern0_0 = arg0; let pattern1_0 = C::value_type(ctx, pattern0_0); if let Some(pattern2_0) = C::u64_from_signed_value(ctx, pattern0_0) { - // Rule at src/isa/s390x/inst.isle line 1999. + // Rule at src/isa/s390x/inst.isle line 2033. let expr0_0 = constructor_ty_ext32(ctx, pattern1_0)?; let expr1_0 = constructor_imm(ctx, expr0_0, pattern2_0)?; return Some(expr1_0); @@ -3471,7 +3540,7 @@ pub fn constructor_put_in_reg_sext32(ctx: &mut C, arg0: Value) -> Op { if let &Opcode::Load = &pattern5_0 { if let Some(()) = C::bigendian(ctx, pattern5_2) { - // Rule at src/isa/s390x/inst.isle line 2001. + // Rule at src/isa/s390x/inst.isle line 2035. let expr0_0 = constructor_sink_load(ctx, pattern3_0)?; let expr1_0 = constructor_sext32_mem(ctx, pattern2_0, &expr0_0)?; return Some(expr1_0); @@ -3479,13 +3548,13 @@ pub fn constructor_put_in_reg_sext32(ctx: &mut C, arg0: Value) -> Op } } } - // Rule at src/isa/s390x/inst.isle line 2003. + // Rule at src/isa/s390x/inst.isle line 2037. let expr0_0 = C::put_in_reg(ctx, pattern0_0); let expr1_0 = constructor_sext32_reg(ctx, pattern2_0, expr0_0)?; return Some(expr1_0); } if let Some(pattern2_0) = C::ty_32_or_64(ctx, pattern1_0) { - // Rule at src/isa/s390x/inst.isle line 2005. + // Rule at src/isa/s390x/inst.isle line 2039. let expr0_0 = C::put_in_reg(ctx, pattern0_0); return Some(expr0_0); } @@ -3497,7 +3566,7 @@ pub fn constructor_put_in_reg_zext64(ctx: &mut C, arg0: Value) -> Op let pattern0_0 = arg0; let pattern1_0 = C::value_type(ctx, pattern0_0); if let Some(pattern2_0) = C::u64_from_value(ctx, pattern0_0) { - // Rule at src/isa/s390x/inst.isle line 2010. + // Rule at src/isa/s390x/inst.isle line 2044. let expr0_0 = constructor_ty_ext64(ctx, pattern1_0)?; let expr1_0 = constructor_imm(ctx, expr0_0, pattern2_0)?; return Some(expr1_0); @@ -3514,7 +3583,7 @@ pub fn constructor_put_in_reg_zext64(ctx: &mut C, arg0: Value) -> Op { if let &Opcode::Load = &pattern5_0 { if let Some(()) = C::bigendian(ctx, pattern5_2) { - // Rule at src/isa/s390x/inst.isle line 2012. + // Rule at src/isa/s390x/inst.isle line 2046. let expr0_0 = constructor_sink_load(ctx, pattern3_0)?; let expr1_0 = constructor_zext64_mem(ctx, pattern2_0, &expr0_0)?; return Some(expr1_0); @@ -3522,13 +3591,13 @@ pub fn constructor_put_in_reg_zext64(ctx: &mut C, arg0: Value) -> Op } } } - // Rule at src/isa/s390x/inst.isle line 2014. + // Rule at src/isa/s390x/inst.isle line 2048. let expr0_0 = C::put_in_reg(ctx, pattern0_0); let expr1_0 = constructor_zext64_reg(ctx, pattern2_0, expr0_0)?; return Some(expr1_0); } if let Some(pattern2_0) = C::gpr64_ty(ctx, pattern1_0) { - // Rule at src/isa/s390x/inst.isle line 2016. + // Rule at src/isa/s390x/inst.isle line 2050. let expr0_0 = C::put_in_reg(ctx, pattern0_0); return Some(expr0_0); } @@ -3540,7 +3609,7 @@ pub fn constructor_put_in_reg_sext64(ctx: &mut C, arg0: Value) -> Op let pattern0_0 = arg0; let pattern1_0 = C::value_type(ctx, pattern0_0); if let Some(pattern2_0) = C::u64_from_signed_value(ctx, pattern0_0) { - // Rule at src/isa/s390x/inst.isle line 2021. + // Rule at src/isa/s390x/inst.isle line 2055. let expr0_0 = constructor_ty_ext64(ctx, pattern1_0)?; let expr1_0 = constructor_imm(ctx, expr0_0, pattern2_0)?; return Some(expr1_0); @@ -3557,7 +3626,7 @@ pub fn constructor_put_in_reg_sext64(ctx: &mut C, arg0: Value) -> Op { if let &Opcode::Load = &pattern5_0 { if let Some(()) = C::bigendian(ctx, pattern5_2) { - // Rule at src/isa/s390x/inst.isle line 2023. + // Rule at src/isa/s390x/inst.isle line 2057. let expr0_0 = constructor_sink_load(ctx, pattern3_0)?; let expr1_0 = constructor_sext64_mem(ctx, pattern2_0, &expr0_0)?; return Some(expr1_0); @@ -3565,13 +3634,13 @@ pub fn constructor_put_in_reg_sext64(ctx: &mut C, arg0: Value) -> Op } } } - // Rule at src/isa/s390x/inst.isle line 2025. + // Rule at src/isa/s390x/inst.isle line 2059. let expr0_0 = C::put_in_reg(ctx, pattern0_0); let expr1_0 = constructor_sext64_reg(ctx, pattern2_0, expr0_0)?; return Some(expr1_0); } if let Some(pattern2_0) = C::gpr64_ty(ctx, pattern1_0) { - // Rule at src/isa/s390x/inst.isle line 2027. + // Rule at src/isa/s390x/inst.isle line 2061. let expr0_0 = C::put_in_reg(ctx, pattern0_0); return Some(expr0_0); } @@ -3586,7 +3655,7 @@ pub fn constructor_put_in_regpair_lo_zext32( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2033. + // Rule at src/isa/s390x/inst.isle line 2067. let expr0_0 = constructor_copy_writable_regpair(ctx, pattern1_0)?; let expr1_0 = constructor_writable_regpair_lo(ctx, &expr0_0)?; let expr2_0 = constructor_emit_put_in_reg_zext32(ctx, expr1_0, pattern0_0)?; @@ -3602,7 +3671,7 @@ pub fn constructor_put_in_regpair_lo_sext32( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2041. + // Rule at src/isa/s390x/inst.isle line 2075. let expr0_0 = constructor_copy_writable_regpair(ctx, pattern1_0)?; let expr1_0 = constructor_writable_regpair_lo(ctx, &expr0_0)?; let expr2_0 = constructor_emit_put_in_reg_sext32(ctx, expr1_0, pattern0_0)?; @@ -3618,7 +3687,7 @@ pub fn constructor_put_in_regpair_lo_zext64( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2049. + // Rule at src/isa/s390x/inst.isle line 2083. let expr0_0 = constructor_copy_writable_regpair(ctx, pattern1_0)?; let expr1_0 = constructor_writable_regpair_lo(ctx, &expr0_0)?; let expr2_0 = constructor_emit_put_in_reg_zext64(ctx, expr1_0, pattern0_0)?; @@ -3634,7 +3703,7 @@ pub fn constructor_put_in_regpair_lo_sext64( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2057. + // Rule at src/isa/s390x/inst.isle line 2091. let expr0_0 = constructor_copy_writable_regpair(ctx, pattern1_0)?; let expr1_0 = constructor_writable_regpair_lo(ctx, &expr0_0)?; let expr2_0 = constructor_emit_put_in_reg_sext64(ctx, expr1_0, pattern0_0)?; @@ -3655,7 +3724,7 @@ pub fn constructor_emit_cmov_imm( let pattern2_0 = arg1; let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 2067. + // Rule at src/isa/s390x/inst.isle line 2101. let expr0_0 = MInst::CMov32SImm16 { rd: pattern2_0, cond: pattern3_0.clone(), @@ -3672,7 +3741,7 @@ pub fn constructor_emit_cmov_imm( let pattern2_0 = arg1; let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 2070. + // Rule at src/isa/s390x/inst.isle line 2104. let expr0_0 = MInst::CMov64SImm16 { rd: pattern2_0, cond: pattern3_0.clone(), @@ -3700,7 +3769,7 @@ pub fn constructor_cmov_imm( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 2076. + // Rule at src/isa/s390x/inst.isle line 2110. let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern3_0)?; let expr1_0 = constructor_emit_cmov_imm(ctx, pattern0_0, expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -3720,7 +3789,7 @@ pub fn constructor_cmov_imm_regpair_lo( let pattern2_0 = arg2; let pattern3_0 = arg3; let pattern4_0 = arg4; - // Rule at src/isa/s390x/inst.isle line 2083. + // Rule at src/isa/s390x/inst.isle line 2117. let expr0_0 = constructor_copy_writable_regpair(ctx, pattern4_0)?; let expr1_0 = constructor_writable_regpair_lo(ctx, &expr0_0)?; let expr2_0 = constructor_emit_cmov_imm(ctx, pattern0_0, expr1_0, pattern2_0, pattern3_0)?; @@ -3743,7 +3812,7 @@ pub fn constructor_cmov_imm_regpair_hi( let pattern2_0 = arg2; let pattern3_0 = arg3; let pattern4_0 = arg4; - // Rule at src/isa/s390x/inst.isle line 2092. + // Rule at src/isa/s390x/inst.isle line 2126. let expr0_0 = constructor_copy_writable_regpair(ctx, pattern4_0)?; let expr1_0 = constructor_writable_regpair_hi(ctx, &expr0_0)?; let expr2_0 = constructor_emit_cmov_imm(ctx, pattern0_0, expr1_0, pattern2_0, pattern3_0)?; @@ -3765,7 +3834,7 @@ pub fn constructor_emit_cmov_reg( let pattern2_0 = arg1; let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 2106. + // Rule at src/isa/s390x/inst.isle line 2140. let expr0_0 = MInst::FpuCMov32 { rd: pattern2_0, cond: pattern3_0.clone(), @@ -3782,7 +3851,7 @@ pub fn constructor_emit_cmov_reg( let pattern2_0 = arg1; let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 2109. + // Rule at src/isa/s390x/inst.isle line 2143. let expr0_0 = MInst::FpuCMov64 { rd: pattern2_0, cond: pattern3_0.clone(), @@ -3799,7 +3868,7 @@ pub fn constructor_emit_cmov_reg( let pattern2_0 = arg1; let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 2100. + // Rule at src/isa/s390x/inst.isle line 2134. let expr0_0 = MInst::CMov32 { rd: pattern2_0, cond: pattern3_0.clone(), @@ -3816,7 +3885,7 @@ pub fn constructor_emit_cmov_reg( let pattern2_0 = arg1; let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 2103. + // Rule at src/isa/s390x/inst.isle line 2137. let expr0_0 = MInst::CMov64 { rd: pattern2_0, cond: pattern3_0.clone(), @@ -3844,7 +3913,7 @@ pub fn constructor_cmov_reg( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 2115. + // Rule at src/isa/s390x/inst.isle line 2149. let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern3_0)?; let expr1_0 = constructor_emit_cmov_reg(ctx, pattern0_0, expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -3865,7 +3934,7 @@ pub fn constructor_trap_if( { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2123. + // Rule at src/isa/s390x/inst.isle line 2157. let expr0_0 = C::emit(ctx, &pattern1_0); let expr1_0 = MInst::TrapIf { cond: pattern2_0.clone(), @@ -3891,7 +3960,7 @@ pub fn constructor_icmps_reg_and_trap( let pattern2_0 = arg2; let pattern3_0 = arg3; let pattern4_0 = arg4; - // Rule at src/isa/s390x/inst.isle line 2129. + // Rule at src/isa/s390x/inst.isle line 2163. let expr0_0 = constructor_cmpop_cmps(ctx, pattern0_0)?; let expr1_0 = MInst::CmpTrapRR { op: expr0_0, @@ -3919,7 +3988,7 @@ pub fn constructor_icmps_simm16_and_trap( let pattern2_0 = arg2; let pattern3_0 = arg3; let pattern4_0 = arg4; - // Rule at src/isa/s390x/inst.isle line 2135. + // Rule at src/isa/s390x/inst.isle line 2169. let expr0_0 = constructor_cmpop_cmps(ctx, pattern0_0)?; let expr1_0 = MInst::CmpTrapRSImm16 { op: expr0_0, @@ -3947,7 +4016,7 @@ pub fn constructor_icmpu_reg_and_trap( let pattern2_0 = arg2; let pattern3_0 = arg3; let pattern4_0 = arg4; - // Rule at src/isa/s390x/inst.isle line 2141. + // Rule at src/isa/s390x/inst.isle line 2175. let expr0_0 = constructor_cmpop_cmpu(ctx, pattern0_0)?; let expr1_0 = MInst::CmpTrapRR { op: expr0_0, @@ -3975,7 +4044,7 @@ pub fn constructor_icmpu_uimm16_and_trap( let pattern2_0 = arg2; let pattern3_0 = arg3; let pattern4_0 = arg4; - // Rule at src/isa/s390x/inst.isle line 2147. + // Rule at src/isa/s390x/inst.isle line 2181. let expr0_0 = constructor_cmpop_cmpu(ctx, pattern0_0)?; let expr1_0 = MInst::CmpTrapRUImm16 { op: expr0_0, @@ -3989,6 +4058,63 @@ pub fn constructor_icmpu_uimm16_and_trap( return Some(expr3_0); } +// Generated as internal constructor for term trap_impl. +pub fn constructor_trap_impl( + ctx: &mut C, + arg0: &TrapCode, +) -> Option { + let pattern0_0 = arg0; + // Rule at src/isa/s390x/inst.isle line 2187. + let expr0_0 = MInst::Trap { + trap_code: pattern0_0.clone(), + }; + let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 }; + return Some(expr1_0); +} + +// Generated as internal constructor for term trap_if_impl. +pub fn constructor_trap_if_impl( + ctx: &mut C, + arg0: &Cond, + arg1: &TrapCode, +) -> Option { + let pattern0_0 = arg0; + let pattern1_0 = arg1; + // Rule at src/isa/s390x/inst.isle line 2191. + let expr0_0 = MInst::TrapIf { + cond: pattern0_0.clone(), + trap_code: pattern1_0.clone(), + }; + let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 }; + return Some(expr1_0); +} + +// Generated as internal constructor for term debugtrap_impl. +pub fn constructor_debugtrap_impl(ctx: &mut C) -> Option { + // Rule at src/isa/s390x/inst.isle line 2195. + let expr0_0 = MInst::Debugtrap; + let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 }; + return Some(expr1_0); +} + +// Generated as internal constructor for term safepoint. +pub fn constructor_safepoint( + ctx: &mut C, + arg0: &SideEffectNoResult, +) -> Option { + let pattern0_0 = arg0; + if let &SideEffectNoResult::Inst { + inst: ref pattern1_0, + } = pattern0_0 + { + // Rule at src/isa/s390x/inst.isle line 2199. + let expr0_0 = C::emit_safepoint(ctx, &pattern1_0); + let expr1_0 = C::value_regs_invalid(ctx); + return Some(expr1_0); + } + return None; +} + // Generated as internal constructor for term bool. pub fn constructor_bool( ctx: &mut C, @@ -3997,7 +4123,7 @@ pub fn constructor_bool( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2160. + // Rule at src/isa/s390x/inst.isle line 2211. let expr0_0 = ProducesBool::ProducesBool { producer: pattern0_0.clone(), cond: pattern1_0.clone(), @@ -4016,7 +4142,7 @@ pub fn constructor_invert_bool( cond: ref pattern1_1, } = pattern0_0 { - // Rule at src/isa/s390x/inst.isle line 2164. + // Rule at src/isa/s390x/inst.isle line 2215. let expr0_0 = C::invert_cond(ctx, &pattern1_1); let expr1_0 = constructor_bool(ctx, &pattern1_0, &expr0_0)?; return Some(expr1_0); @@ -4032,7 +4158,7 @@ pub fn constructor_emit_producer(ctx: &mut C, arg0: &ProducesFlags) result: pattern1_1, } = pattern0_0 { - // Rule at src/isa/s390x/inst.isle line 2173. + // Rule at src/isa/s390x/inst.isle line 2224. let expr0_0 = C::emit(ctx, &pattern1_0); return Some(expr0_0); } @@ -4047,7 +4173,7 @@ pub fn constructor_emit_consumer(ctx: &mut C, arg0: &ConsumesFlags) result: pattern1_1, } = pattern0_0 { - // Rule at src/isa/s390x/inst.isle line 2175. + // Rule at src/isa/s390x/inst.isle line 2226. let expr0_0 = C::emit(ctx, &pattern1_0); return Some(expr0_0); } @@ -4071,7 +4197,7 @@ pub fn constructor_select_bool_reg( { let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 2179. + // Rule at src/isa/s390x/inst.isle line 2230. let expr0_0 = C::temp_writable_reg(ctx, pattern0_0); let expr1_0 = constructor_emit_producer(ctx, &pattern2_0)?; let expr2_0 = constructor_emit_mov(ctx, pattern0_0, expr0_0, pattern4_0)?; @@ -4100,7 +4226,7 @@ pub fn constructor_select_bool_imm( { let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 2188. + // Rule at src/isa/s390x/inst.isle line 2239. let expr0_0 = C::temp_writable_reg(ctx, pattern0_0); let expr1_0 = constructor_emit_producer(ctx, &pattern2_0)?; let expr2_0 = constructor_emit_imm(ctx, pattern0_0, expr0_0, pattern4_0)?; @@ -4121,7 +4247,7 @@ pub fn constructor_lower_bool( let pattern0_0 = arg0; if pattern0_0 == B1 { let pattern2_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2198. + // Rule at src/isa/s390x/inst.isle line 2249. let expr0_0: Type = B1; let expr1_0: i16 = 1; let expr2_0: u64 = 0; @@ -4130,7 +4256,7 @@ pub fn constructor_lower_bool( } if pattern0_0 == B8 { let pattern2_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2199. + // Rule at src/isa/s390x/inst.isle line 2250. let expr0_0: Type = B8; let expr1_0: i16 = -1; let expr2_0: u64 = 0; @@ -4139,7 +4265,7 @@ pub fn constructor_lower_bool( } if pattern0_0 == B16 { let pattern2_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2200. + // Rule at src/isa/s390x/inst.isle line 2251. let expr0_0: Type = B16; let expr1_0: i16 = -1; let expr2_0: u64 = 0; @@ -4148,7 +4274,7 @@ pub fn constructor_lower_bool( } if pattern0_0 == B32 { let pattern2_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2201. + // Rule at src/isa/s390x/inst.isle line 2252. let expr0_0: Type = B32; let expr1_0: i16 = -1; let expr2_0: u64 = 0; @@ -4157,7 +4283,7 @@ pub fn constructor_lower_bool( } if pattern0_0 == B64 { let pattern2_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2202. + // Rule at src/isa/s390x/inst.isle line 2253. let expr0_0: Type = B64; let expr1_0: i16 = -1; let expr2_0: u64 = 0; @@ -4167,12 +4293,77 @@ pub fn constructor_lower_bool( return None; } +// Generated as internal constructor for term cond_br_bool. +pub fn constructor_cond_br_bool( + ctx: &mut C, + arg0: &ProducesBool, + arg1: MachLabel, + arg2: MachLabel, +) -> Option { + let pattern0_0 = arg0; + if let &ProducesBool::ProducesBool { + producer: ref pattern1_0, + cond: ref pattern1_1, + } = pattern0_0 + { + let pattern2_0 = arg1; + let pattern3_0 = arg2; + // Rule at src/isa/s390x/inst.isle line 2257. + let expr0_0 = constructor_emit_producer(ctx, &pattern1_0)?; + let expr1_0 = constructor_cond_br(ctx, pattern2_0, pattern3_0, &pattern1_1)?; + return Some(expr1_0); + } + return None; +} + +// Generated as internal constructor for term oneway_cond_br_bool. +pub fn constructor_oneway_cond_br_bool( + ctx: &mut C, + arg0: &ProducesBool, + arg1: MachLabel, +) -> Option { + let pattern0_0 = arg0; + if let &ProducesBool::ProducesBool { + producer: ref pattern1_0, + cond: ref pattern1_1, + } = pattern0_0 + { + let pattern2_0 = arg1; + // Rule at src/isa/s390x/inst.isle line 2263. + let expr0_0 = constructor_emit_producer(ctx, &pattern1_0)?; + let expr1_0 = constructor_oneway_cond_br(ctx, pattern2_0, &pattern1_1)?; + return Some(expr1_0); + } + return None; +} + +// Generated as internal constructor for term trap_if_bool. +pub fn constructor_trap_if_bool( + ctx: &mut C, + arg0: &ProducesBool, + arg1: &TrapCode, +) -> Option { + let pattern0_0 = arg0; + if let &ProducesBool::ProducesBool { + producer: ref pattern1_0, + cond: ref pattern1_1, + } = pattern0_0 + { + let pattern2_0 = arg1; + // Rule at src/isa/s390x/inst.isle line 2269. + let expr0_0 = constructor_emit_producer(ctx, &pattern1_0)?; + let expr1_0 = constructor_trap_if_impl(ctx, &pattern1_1, pattern2_0)?; + return Some(expr1_0); + } + return None; +} + // Generated as internal constructor for term clz_reg. pub fn constructor_clz_reg(ctx: &mut C, arg0: i16, arg1: Reg) -> Option { let pattern0_0 = arg0; if pattern0_0 == 64 { let pattern2_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2211. + // Rule at src/isa/s390x/inst.isle line 2280. let expr0_0 = constructor_temp_writable_regpair(ctx)?; let expr1_0 = MInst::Flogr { rn: pattern2_0 }; let expr2_0 = C::emit(ctx, &expr1_0); @@ -4180,7 +4371,7 @@ pub fn constructor_clz_reg(ctx: &mut C, arg0: i16, arg1: Reg) -> Opt return Some(expr3_0); } let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2220. + // Rule at src/isa/s390x/inst.isle line 2289. let expr0_0 = constructor_temp_writable_regpair(ctx)?; let expr1_0 = MInst::Flogr { rn: pattern1_0 }; let expr2_0 = C::emit(ctx, &expr1_0); @@ -4201,22 +4392,22 @@ pub fn constructor_clz_reg(ctx: &mut C, arg0: i16, arg1: Reg) -> Opt pub fn constructor_aluop_add(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I8 { - // Rule at src/isa/s390x/inst.isle line 2231. + // Rule at src/isa/s390x/inst.isle line 2300. let expr0_0 = ALUOp::Add32; return Some(expr0_0); } if pattern0_0 == I16 { - // Rule at src/isa/s390x/inst.isle line 2232. + // Rule at src/isa/s390x/inst.isle line 2301. let expr0_0 = ALUOp::Add32; return Some(expr0_0); } if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2233. + // Rule at src/isa/s390x/inst.isle line 2302. let expr0_0 = ALUOp::Add32; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2234. + // Rule at src/isa/s390x/inst.isle line 2303. let expr0_0 = ALUOp::Add64; return Some(expr0_0); } @@ -4227,17 +4418,17 @@ pub fn constructor_aluop_add(ctx: &mut C, arg0: Type) -> Option(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I16 { - // Rule at src/isa/s390x/inst.isle line 2237. + // Rule at src/isa/s390x/inst.isle line 2306. let expr0_0 = ALUOp::Add32Ext16; return Some(expr0_0); } if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2238. + // Rule at src/isa/s390x/inst.isle line 2307. let expr0_0 = ALUOp::Add32Ext16; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2239. + // Rule at src/isa/s390x/inst.isle line 2308. let expr0_0 = ALUOp::Add64Ext16; return Some(expr0_0); } @@ -4248,7 +4439,7 @@ pub fn constructor_aluop_add_sext16(ctx: &mut C, arg0: Type) -> Opti pub fn constructor_aluop_add_sext32(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2242. + // Rule at src/isa/s390x/inst.isle line 2311. let expr0_0 = ALUOp::Add64Ext32; return Some(expr0_0); } @@ -4265,7 +4456,7 @@ pub fn constructor_add_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2245. + // Rule at src/isa/s390x/inst.isle line 2314. let expr0_0 = constructor_aluop_add(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4281,7 +4472,7 @@ pub fn constructor_add_reg_sext32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2248. + // Rule at src/isa/s390x/inst.isle line 2317. let expr0_0 = constructor_aluop_add_sext32(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4297,7 +4488,7 @@ pub fn constructor_add_simm16( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2251. + // Rule at src/isa/s390x/inst.isle line 2320. let expr0_0 = constructor_aluop_add(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rrsimm16(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4313,7 +4504,7 @@ pub fn constructor_add_simm32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2254. + // Rule at src/isa/s390x/inst.isle line 2323. let expr0_0 = constructor_aluop_add(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rsimm32(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4329,7 +4520,7 @@ pub fn constructor_add_mem( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2257. + // Rule at src/isa/s390x/inst.isle line 2326. let expr0_0 = constructor_aluop_add(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4345,7 +4536,7 @@ pub fn constructor_add_mem_sext16( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2260. + // Rule at src/isa/s390x/inst.isle line 2329. let expr0_0 = constructor_aluop_add_sext16(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4361,7 +4552,7 @@ pub fn constructor_add_mem_sext32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2263. + // Rule at src/isa/s390x/inst.isle line 2332. let expr0_0 = constructor_aluop_add_sext32(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4371,12 +4562,12 @@ pub fn constructor_add_mem_sext32( pub fn constructor_aluop_add_logical(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2269. + // Rule at src/isa/s390x/inst.isle line 2338. let expr0_0 = ALUOp::AddLogical32; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2270. + // Rule at src/isa/s390x/inst.isle line 2339. let expr0_0 = ALUOp::AddLogical64; return Some(expr0_0); } @@ -4387,7 +4578,7 @@ pub fn constructor_aluop_add_logical(ctx: &mut C, arg0: Type) -> Opt pub fn constructor_aluop_add_logical_zext32(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2273. + // Rule at src/isa/s390x/inst.isle line 2342. let expr0_0 = ALUOp::AddLogical64Ext32; return Some(expr0_0); } @@ -4404,7 +4595,7 @@ pub fn constructor_add_logical_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2276. + // Rule at src/isa/s390x/inst.isle line 2345. let expr0_0 = constructor_aluop_add_logical(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4420,7 +4611,7 @@ pub fn constructor_add_logical_reg_zext32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2279. + // Rule at src/isa/s390x/inst.isle line 2348. let expr0_0 = constructor_aluop_add_logical_zext32(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4436,7 +4627,7 @@ pub fn constructor_add_logical_zimm32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2282. + // Rule at src/isa/s390x/inst.isle line 2351. let expr0_0 = constructor_aluop_add_logical(ctx, pattern0_0)?; let expr1_0 = constructor_alu_ruimm32(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4452,7 +4643,7 @@ pub fn constructor_add_logical_mem( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2285. + // Rule at src/isa/s390x/inst.isle line 2354. let expr0_0 = constructor_aluop_add_logical(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4468,7 +4659,7 @@ pub fn constructor_add_logical_mem_zext32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2288. + // Rule at src/isa/s390x/inst.isle line 2357. let expr0_0 = constructor_aluop_add_logical_zext32(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4478,22 +4669,22 @@ pub fn constructor_add_logical_mem_zext32( pub fn constructor_aluop_sub(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I8 { - // Rule at src/isa/s390x/inst.isle line 2294. + // Rule at src/isa/s390x/inst.isle line 2363. let expr0_0 = ALUOp::Sub32; return Some(expr0_0); } if pattern0_0 == I16 { - // Rule at src/isa/s390x/inst.isle line 2295. + // Rule at src/isa/s390x/inst.isle line 2364. let expr0_0 = ALUOp::Sub32; return Some(expr0_0); } if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2296. + // Rule at src/isa/s390x/inst.isle line 2365. let expr0_0 = ALUOp::Sub32; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2297. + // Rule at src/isa/s390x/inst.isle line 2366. let expr0_0 = ALUOp::Sub64; return Some(expr0_0); } @@ -4504,17 +4695,17 @@ pub fn constructor_aluop_sub(ctx: &mut C, arg0: Type) -> Option(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I16 { - // Rule at src/isa/s390x/inst.isle line 2300. + // Rule at src/isa/s390x/inst.isle line 2369. let expr0_0 = ALUOp::Sub32Ext16; return Some(expr0_0); } if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2301. + // Rule at src/isa/s390x/inst.isle line 2370. let expr0_0 = ALUOp::Sub32Ext16; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2302. + // Rule at src/isa/s390x/inst.isle line 2371. let expr0_0 = ALUOp::Sub64Ext16; return Some(expr0_0); } @@ -4525,7 +4716,7 @@ pub fn constructor_aluop_sub_sext16(ctx: &mut C, arg0: Type) -> Opti pub fn constructor_aluop_sub_sext32(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2305. + // Rule at src/isa/s390x/inst.isle line 2374. let expr0_0 = ALUOp::Sub64Ext32; return Some(expr0_0); } @@ -4542,7 +4733,7 @@ pub fn constructor_sub_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2308. + // Rule at src/isa/s390x/inst.isle line 2377. let expr0_0 = constructor_aluop_sub(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4558,7 +4749,7 @@ pub fn constructor_sub_reg_sext32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2311. + // Rule at src/isa/s390x/inst.isle line 2380. let expr0_0 = constructor_aluop_sub_sext32(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4574,7 +4765,7 @@ pub fn constructor_sub_mem( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2314. + // Rule at src/isa/s390x/inst.isle line 2383. let expr0_0 = constructor_aluop_sub(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4590,7 +4781,7 @@ pub fn constructor_sub_mem_sext16( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2317. + // Rule at src/isa/s390x/inst.isle line 2386. let expr0_0 = constructor_aluop_sub_sext16(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4606,7 +4797,7 @@ pub fn constructor_sub_mem_sext32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2320. + // Rule at src/isa/s390x/inst.isle line 2389. let expr0_0 = constructor_aluop_sub_sext32(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4616,12 +4807,12 @@ pub fn constructor_sub_mem_sext32( pub fn constructor_aluop_sub_logical(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2326. + // Rule at src/isa/s390x/inst.isle line 2395. let expr0_0 = ALUOp::SubLogical32; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2327. + // Rule at src/isa/s390x/inst.isle line 2396. let expr0_0 = ALUOp::SubLogical64; return Some(expr0_0); } @@ -4632,7 +4823,7 @@ pub fn constructor_aluop_sub_logical(ctx: &mut C, arg0: Type) -> Opt pub fn constructor_aluop_sub_logical_zext32(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2330. + // Rule at src/isa/s390x/inst.isle line 2399. let expr0_0 = ALUOp::SubLogical64Ext32; return Some(expr0_0); } @@ -4649,7 +4840,7 @@ pub fn constructor_sub_logical_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2333. + // Rule at src/isa/s390x/inst.isle line 2402. let expr0_0 = constructor_aluop_sub_logical(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4665,7 +4856,7 @@ pub fn constructor_sub_logical_reg_zext32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2336. + // Rule at src/isa/s390x/inst.isle line 2405. let expr0_0 = constructor_aluop_sub_logical_zext32(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4681,7 +4872,7 @@ pub fn constructor_sub_logical_zimm32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2339. + // Rule at src/isa/s390x/inst.isle line 2408. let expr0_0 = constructor_aluop_sub_logical(ctx, pattern0_0)?; let expr1_0 = constructor_alu_ruimm32(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4697,7 +4888,7 @@ pub fn constructor_sub_logical_mem( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2342. + // Rule at src/isa/s390x/inst.isle line 2411. let expr0_0 = constructor_aluop_sub_logical(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4713,7 +4904,7 @@ pub fn constructor_sub_logical_mem_zext32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2345. + // Rule at src/isa/s390x/inst.isle line 2414. let expr0_0 = constructor_aluop_sub_logical(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4723,22 +4914,22 @@ pub fn constructor_sub_logical_mem_zext32( pub fn constructor_aluop_mul(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I8 { - // Rule at src/isa/s390x/inst.isle line 2351. + // Rule at src/isa/s390x/inst.isle line 2420. let expr0_0 = ALUOp::Mul32; return Some(expr0_0); } if pattern0_0 == I16 { - // Rule at src/isa/s390x/inst.isle line 2352. + // Rule at src/isa/s390x/inst.isle line 2421. let expr0_0 = ALUOp::Mul32; return Some(expr0_0); } if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2353. + // Rule at src/isa/s390x/inst.isle line 2422. let expr0_0 = ALUOp::Mul32; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2354. + // Rule at src/isa/s390x/inst.isle line 2423. let expr0_0 = ALUOp::Mul64; return Some(expr0_0); } @@ -4749,17 +4940,17 @@ pub fn constructor_aluop_mul(ctx: &mut C, arg0: Type) -> Option(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I16 { - // Rule at src/isa/s390x/inst.isle line 2357. + // Rule at src/isa/s390x/inst.isle line 2426. let expr0_0 = ALUOp::Mul32Ext16; return Some(expr0_0); } if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2358. + // Rule at src/isa/s390x/inst.isle line 2427. let expr0_0 = ALUOp::Mul32Ext16; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2359. + // Rule at src/isa/s390x/inst.isle line 2428. let expr0_0 = ALUOp::Mul64Ext16; return Some(expr0_0); } @@ -4770,7 +4961,7 @@ pub fn constructor_aluop_mul_sext16(ctx: &mut C, arg0: Type) -> Opti pub fn constructor_aluop_mul_sext32(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2362. + // Rule at src/isa/s390x/inst.isle line 2431. let expr0_0 = ALUOp::Mul64Ext32; return Some(expr0_0); } @@ -4787,7 +4978,7 @@ pub fn constructor_mul_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2365. + // Rule at src/isa/s390x/inst.isle line 2434. let expr0_0 = constructor_aluop_mul(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4803,7 +4994,7 @@ pub fn constructor_mul_reg_sext32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2368. + // Rule at src/isa/s390x/inst.isle line 2437. let expr0_0 = constructor_aluop_mul_sext32(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4819,7 +5010,7 @@ pub fn constructor_mul_simm16( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2371. + // Rule at src/isa/s390x/inst.isle line 2440. let expr0_0 = constructor_aluop_mul(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rsimm16(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4835,7 +5026,7 @@ pub fn constructor_mul_simm32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2374. + // Rule at src/isa/s390x/inst.isle line 2443. let expr0_0 = constructor_aluop_mul(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rsimm32(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4851,7 +5042,7 @@ pub fn constructor_mul_mem( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2377. + // Rule at src/isa/s390x/inst.isle line 2446. let expr0_0 = constructor_aluop_mul(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4867,7 +5058,7 @@ pub fn constructor_mul_mem_sext16( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2380. + // Rule at src/isa/s390x/inst.isle line 2449. let expr0_0 = constructor_aluop_mul_sext16(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4883,7 +5074,7 @@ pub fn constructor_mul_mem_sext32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2383. + // Rule at src/isa/s390x/inst.isle line 2452. let expr0_0 = constructor_aluop_mul_sext32(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4900,14 +5091,14 @@ pub fn constructor_udivmod( if pattern0_0 == I32 { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2389. + // Rule at src/isa/s390x/inst.isle line 2458. let expr0_0 = constructor_udivmod32(ctx, pattern2_0, pattern3_0)?; return Some(expr0_0); } if pattern0_0 == I64 { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2390. + // Rule at src/isa/s390x/inst.isle line 2459. let expr0_0 = constructor_udivmod64(ctx, pattern2_0, pattern3_0)?; return Some(expr0_0); } @@ -4925,14 +5116,14 @@ pub fn constructor_sdivmod( if pattern0_0 == I32 { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2396. + // Rule at src/isa/s390x/inst.isle line 2465. let expr0_0 = constructor_sdivmod32(ctx, pattern2_0, pattern3_0)?; return Some(expr0_0); } if pattern0_0 == I64 { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2397. + // Rule at src/isa/s390x/inst.isle line 2466. let expr0_0 = constructor_sdivmod64(ctx, pattern2_0, pattern3_0)?; return Some(expr0_0); } @@ -4943,12 +5134,12 @@ pub fn constructor_sdivmod( pub fn constructor_aluop_and(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) { - // Rule at src/isa/s390x/inst.isle line 2403. + // Rule at src/isa/s390x/inst.isle line 2472. let expr0_0 = ALUOp::And32; return Some(expr0_0); } if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) { - // Rule at src/isa/s390x/inst.isle line 2404. + // Rule at src/isa/s390x/inst.isle line 2473. let expr0_0 = ALUOp::And64; return Some(expr0_0); } @@ -4965,7 +5156,7 @@ pub fn constructor_and_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2407. + // Rule at src/isa/s390x/inst.isle line 2476. let expr0_0 = constructor_aluop_and(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -4981,7 +5172,7 @@ pub fn constructor_and_uimm16shifted( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2410. + // Rule at src/isa/s390x/inst.isle line 2479. let expr0_0 = constructor_aluop_and(ctx, pattern0_0)?; let expr1_0 = constructor_alu_ruimm16shifted(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; @@ -4998,7 +5189,7 @@ pub fn constructor_and_uimm32shifted( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2413. + // Rule at src/isa/s390x/inst.isle line 2482. let expr0_0 = constructor_aluop_and(ctx, pattern0_0)?; let expr1_0 = constructor_alu_ruimm32shifted(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; @@ -5015,7 +5206,7 @@ pub fn constructor_and_mem( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2416. + // Rule at src/isa/s390x/inst.isle line 2485. let expr0_0 = constructor_aluop_and(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -5025,12 +5216,12 @@ pub fn constructor_and_mem( pub fn constructor_aluop_or(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) { - // Rule at src/isa/s390x/inst.isle line 2422. + // Rule at src/isa/s390x/inst.isle line 2491. let expr0_0 = ALUOp::Orr32; return Some(expr0_0); } if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) { - // Rule at src/isa/s390x/inst.isle line 2423. + // Rule at src/isa/s390x/inst.isle line 2492. let expr0_0 = ALUOp::Orr64; return Some(expr0_0); } @@ -5047,7 +5238,7 @@ pub fn constructor_or_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2426. + // Rule at src/isa/s390x/inst.isle line 2495. let expr0_0 = constructor_aluop_or(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -5063,7 +5254,7 @@ pub fn constructor_or_uimm16shifted( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2429. + // Rule at src/isa/s390x/inst.isle line 2498. let expr0_0 = constructor_aluop_or(ctx, pattern0_0)?; let expr1_0 = constructor_alu_ruimm16shifted(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; @@ -5080,7 +5271,7 @@ pub fn constructor_or_uimm32shifted( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2432. + // Rule at src/isa/s390x/inst.isle line 2501. let expr0_0 = constructor_aluop_or(ctx, pattern0_0)?; let expr1_0 = constructor_alu_ruimm32shifted(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; @@ -5097,7 +5288,7 @@ pub fn constructor_or_mem( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2435. + // Rule at src/isa/s390x/inst.isle line 2504. let expr0_0 = constructor_aluop_or(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -5107,12 +5298,12 @@ pub fn constructor_or_mem( pub fn constructor_aluop_xor(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) { - // Rule at src/isa/s390x/inst.isle line 2441. + // Rule at src/isa/s390x/inst.isle line 2510. let expr0_0 = ALUOp::Xor32; return Some(expr0_0); } if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) { - // Rule at src/isa/s390x/inst.isle line 2442. + // Rule at src/isa/s390x/inst.isle line 2511. let expr0_0 = ALUOp::Xor64; return Some(expr0_0); } @@ -5129,7 +5320,7 @@ pub fn constructor_xor_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2445. + // Rule at src/isa/s390x/inst.isle line 2514. let expr0_0 = constructor_aluop_xor(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -5145,7 +5336,7 @@ pub fn constructor_xor_uimm32shifted( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2448. + // Rule at src/isa/s390x/inst.isle line 2517. let expr0_0 = constructor_aluop_xor(ctx, pattern0_0)?; let expr1_0 = constructor_alu_ruimm32shifted(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; @@ -5162,7 +5353,7 @@ pub fn constructor_xor_mem( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2451. + // Rule at src/isa/s390x/inst.isle line 2520. let expr0_0 = constructor_aluop_xor(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -5173,7 +5364,7 @@ pub fn constructor_not_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> Op let pattern0_0 = arg0; if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) { let pattern2_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2457. + // Rule at src/isa/s390x/inst.isle line 2526. let expr0_0: u32 = 4294967295; let expr1_0: u8 = 0; let expr2_0 = C::uimm32shifted(ctx, expr0_0, expr1_0); @@ -5182,7 +5373,7 @@ pub fn constructor_not_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> Op } if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) { let pattern2_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2459. + // Rule at src/isa/s390x/inst.isle line 2528. let expr0_0: u32 = 4294967295; let expr1_0: u8 = 0; let expr2_0 = C::uimm32shifted(ctx, expr0_0, expr1_0); @@ -5200,12 +5391,12 @@ pub fn constructor_not_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> Op pub fn constructor_aluop_and_not(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) { - // Rule at src/isa/s390x/inst.isle line 2468. + // Rule at src/isa/s390x/inst.isle line 2537. let expr0_0 = ALUOp::AndNot32; return Some(expr0_0); } if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) { - // Rule at src/isa/s390x/inst.isle line 2469. + // Rule at src/isa/s390x/inst.isle line 2538. let expr0_0 = ALUOp::AndNot64; return Some(expr0_0); } @@ -5222,7 +5413,7 @@ pub fn constructor_and_not_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2472. + // Rule at src/isa/s390x/inst.isle line 2541. let expr0_0 = constructor_aluop_and_not(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -5232,12 +5423,12 @@ pub fn constructor_and_not_reg( pub fn constructor_aluop_or_not(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) { - // Rule at src/isa/s390x/inst.isle line 2478. + // Rule at src/isa/s390x/inst.isle line 2547. let expr0_0 = ALUOp::OrrNot32; return Some(expr0_0); } if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) { - // Rule at src/isa/s390x/inst.isle line 2479. + // Rule at src/isa/s390x/inst.isle line 2548. let expr0_0 = ALUOp::OrrNot64; return Some(expr0_0); } @@ -5254,7 +5445,7 @@ pub fn constructor_or_not_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2482. + // Rule at src/isa/s390x/inst.isle line 2551. let expr0_0 = constructor_aluop_or_not(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -5264,12 +5455,12 @@ pub fn constructor_or_not_reg( pub fn constructor_aluop_xor_not(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) { - // Rule at src/isa/s390x/inst.isle line 2488. + // Rule at src/isa/s390x/inst.isle line 2557. let expr0_0 = ALUOp::XorNot32; return Some(expr0_0); } if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) { - // Rule at src/isa/s390x/inst.isle line 2489. + // Rule at src/isa/s390x/inst.isle line 2558. let expr0_0 = ALUOp::XorNot64; return Some(expr0_0); } @@ -5286,7 +5477,7 @@ pub fn constructor_xor_not_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2492. + // Rule at src/isa/s390x/inst.isle line 2561. let expr0_0 = constructor_aluop_xor_not(ctx, pattern0_0)?; let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -5296,12 +5487,12 @@ pub fn constructor_xor_not_reg( pub fn constructor_unaryop_abs(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2498. + // Rule at src/isa/s390x/inst.isle line 2567. let expr0_0 = UnaryOp::Abs32; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2499. + // Rule at src/isa/s390x/inst.isle line 2568. let expr0_0 = UnaryOp::Abs64; return Some(expr0_0); } @@ -5312,7 +5503,7 @@ pub fn constructor_unaryop_abs(ctx: &mut C, arg0: Type) -> Option(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2502. + // Rule at src/isa/s390x/inst.isle line 2571. let expr0_0 = UnaryOp::Abs64Ext32; return Some(expr0_0); } @@ -5323,7 +5514,7 @@ pub fn constructor_unaryop_abs_sext32(ctx: &mut C, arg0: Type) -> Op pub fn constructor_abs_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2505. + // Rule at src/isa/s390x/inst.isle line 2574. let expr0_0 = constructor_unaryop_abs(ctx, pattern0_0)?; let expr1_0 = constructor_unary_rr(ctx, pattern0_0, &expr0_0, pattern1_0)?; return Some(expr1_0); @@ -5333,7 +5524,7 @@ pub fn constructor_abs_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> Op pub fn constructor_abs_reg_sext32(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2508. + // Rule at src/isa/s390x/inst.isle line 2577. let expr0_0 = constructor_unaryop_abs_sext32(ctx, pattern0_0)?; let expr1_0 = constructor_unary_rr(ctx, pattern0_0, &expr0_0, pattern1_0)?; return Some(expr1_0); @@ -5343,22 +5534,22 @@ pub fn constructor_abs_reg_sext32(ctx: &mut C, arg0: Type, arg1: Reg pub fn constructor_unaryop_neg(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I8 { - // Rule at src/isa/s390x/inst.isle line 2514. + // Rule at src/isa/s390x/inst.isle line 2583. let expr0_0 = UnaryOp::Neg32; return Some(expr0_0); } if pattern0_0 == I16 { - // Rule at src/isa/s390x/inst.isle line 2515. + // Rule at src/isa/s390x/inst.isle line 2584. let expr0_0 = UnaryOp::Neg32; return Some(expr0_0); } if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2516. + // Rule at src/isa/s390x/inst.isle line 2585. let expr0_0 = UnaryOp::Neg32; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2517. + // Rule at src/isa/s390x/inst.isle line 2586. let expr0_0 = UnaryOp::Neg64; return Some(expr0_0); } @@ -5369,7 +5560,7 @@ pub fn constructor_unaryop_neg(ctx: &mut C, arg0: Type) -> Option(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2520. + // Rule at src/isa/s390x/inst.isle line 2589. let expr0_0 = UnaryOp::Neg64Ext32; return Some(expr0_0); } @@ -5380,7 +5571,7 @@ pub fn constructor_unaryop_neg_sext32(ctx: &mut C, arg0: Type) -> Op pub fn constructor_neg_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2523. + // Rule at src/isa/s390x/inst.isle line 2592. let expr0_0 = constructor_unaryop_neg(ctx, pattern0_0)?; let expr1_0 = constructor_unary_rr(ctx, pattern0_0, &expr0_0, pattern1_0)?; return Some(expr1_0); @@ -5390,7 +5581,7 @@ pub fn constructor_neg_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> Op pub fn constructor_neg_reg_sext32(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2526. + // Rule at src/isa/s390x/inst.isle line 2595. let expr0_0 = constructor_unaryop_neg_sext32(ctx, pattern0_0)?; let expr1_0 = constructor_unary_rr(ctx, pattern0_0, &expr0_0, pattern1_0)?; return Some(expr1_0); @@ -5400,12 +5591,12 @@ pub fn constructor_neg_reg_sext32(ctx: &mut C, arg0: Type, arg1: Reg pub fn constructor_shiftop_rot(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2532. + // Rule at src/isa/s390x/inst.isle line 2601. let expr0_0 = ShiftOp::RotL32; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2533. + // Rule at src/isa/s390x/inst.isle line 2602. let expr0_0 = ShiftOp::RotL64; return Some(expr0_0); } @@ -5422,7 +5613,7 @@ pub fn constructor_rot_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2536. + // Rule at src/isa/s390x/inst.isle line 2605. let expr0_0 = constructor_shiftop_rot(ctx, pattern0_0)?; let expr1_0: u8 = 0; let expr2_0 = constructor_shift_rr(ctx, pattern0_0, &expr0_0, pattern1_0, expr1_0, pattern2_0)?; @@ -5439,7 +5630,7 @@ pub fn constructor_rot_imm( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2540. + // Rule at src/isa/s390x/inst.isle line 2609. let expr0_0 = constructor_shiftop_rot(ctx, pattern0_0)?; let expr1_0 = C::zero_reg(ctx); let expr2_0 = constructor_shift_rr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0, expr1_0)?; @@ -5450,22 +5641,22 @@ pub fn constructor_rot_imm( pub fn constructor_shiftop_lshl(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I8 { - // Rule at src/isa/s390x/inst.isle line 2547. + // Rule at src/isa/s390x/inst.isle line 2616. let expr0_0 = ShiftOp::LShL32; return Some(expr0_0); } if pattern0_0 == I16 { - // Rule at src/isa/s390x/inst.isle line 2548. + // Rule at src/isa/s390x/inst.isle line 2617. let expr0_0 = ShiftOp::LShL32; return Some(expr0_0); } if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2549. + // Rule at src/isa/s390x/inst.isle line 2618. let expr0_0 = ShiftOp::LShL32; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2550. + // Rule at src/isa/s390x/inst.isle line 2619. let expr0_0 = ShiftOp::LShL64; return Some(expr0_0); } @@ -5482,7 +5673,7 @@ pub fn constructor_lshl_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2553. + // Rule at src/isa/s390x/inst.isle line 2622. let expr0_0 = constructor_shiftop_lshl(ctx, pattern0_0)?; let expr1_0: u8 = 0; let expr2_0 = constructor_shift_rr(ctx, pattern0_0, &expr0_0, pattern1_0, expr1_0, pattern2_0)?; @@ -5499,7 +5690,7 @@ pub fn constructor_lshl_imm( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2557. + // Rule at src/isa/s390x/inst.isle line 2626. let expr0_0 = constructor_shiftop_lshl(ctx, pattern0_0)?; let expr1_0 = C::zero_reg(ctx); let expr2_0 = constructor_shift_rr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0, expr1_0)?; @@ -5510,12 +5701,12 @@ pub fn constructor_lshl_imm( pub fn constructor_shiftop_lshr(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2564. + // Rule at src/isa/s390x/inst.isle line 2633. let expr0_0 = ShiftOp::LShR32; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2565. + // Rule at src/isa/s390x/inst.isle line 2634. let expr0_0 = ShiftOp::LShR64; return Some(expr0_0); } @@ -5532,7 +5723,7 @@ pub fn constructor_lshr_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2568. + // Rule at src/isa/s390x/inst.isle line 2637. let expr0_0 = constructor_shiftop_lshr(ctx, pattern0_0)?; let expr1_0: u8 = 0; let expr2_0 = constructor_shift_rr(ctx, pattern0_0, &expr0_0, pattern1_0, expr1_0, pattern2_0)?; @@ -5549,7 +5740,7 @@ pub fn constructor_lshr_imm( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2572. + // Rule at src/isa/s390x/inst.isle line 2641. let expr0_0 = constructor_shiftop_lshr(ctx, pattern0_0)?; let expr1_0 = C::zero_reg(ctx); let expr2_0 = constructor_shift_rr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0, expr1_0)?; @@ -5560,12 +5751,12 @@ pub fn constructor_lshr_imm( pub fn constructor_shiftop_ashr(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2579. + // Rule at src/isa/s390x/inst.isle line 2648. let expr0_0 = ShiftOp::AShR32; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2580. + // Rule at src/isa/s390x/inst.isle line 2649. let expr0_0 = ShiftOp::AShR64; return Some(expr0_0); } @@ -5582,7 +5773,7 @@ pub fn constructor_ashr_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2583. + // Rule at src/isa/s390x/inst.isle line 2652. let expr0_0 = constructor_shiftop_ashr(ctx, pattern0_0)?; let expr1_0: u8 = 0; let expr2_0 = constructor_shift_rr(ctx, pattern0_0, &expr0_0, pattern1_0, expr1_0, pattern2_0)?; @@ -5599,7 +5790,7 @@ pub fn constructor_ashr_imm( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2587. + // Rule at src/isa/s390x/inst.isle line 2656. let expr0_0 = constructor_shiftop_ashr(ctx, pattern0_0)?; let expr1_0 = C::zero_reg(ctx); let expr2_0 = constructor_shift_rr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0, expr1_0)?; @@ -5609,7 +5800,7 @@ pub fn constructor_ashr_imm( // Generated as internal constructor for term popcnt_byte. pub fn constructor_popcnt_byte(ctx: &mut C, arg0: Reg) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/s390x/inst.isle line 2594. + // Rule at src/isa/s390x/inst.isle line 2663. let expr0_0: Type = I64; let expr1_0 = UnaryOp::PopcntByte; let expr2_0 = constructor_unary_rr(ctx, expr0_0, &expr1_0, pattern0_0)?; @@ -5619,7 +5810,7 @@ pub fn constructor_popcnt_byte(ctx: &mut C, arg0: Reg) -> Option(ctx: &mut C, arg0: Reg) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/s390x/inst.isle line 2597. + // Rule at src/isa/s390x/inst.isle line 2666. let expr0_0: Type = I64; let expr1_0 = UnaryOp::PopcntReg; let expr2_0 = constructor_unary_rr(ctx, expr0_0, &expr1_0, pattern0_0)?; @@ -5637,7 +5828,7 @@ pub fn constructor_atomic_rmw_and( if pattern0_0 == I32 { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2603. + // Rule at src/isa/s390x/inst.isle line 2672. let expr0_0: Type = I32; let expr1_0 = ALUOp::And32; let expr2_0 = constructor_atomic_rmw_impl(ctx, expr0_0, &expr1_0, pattern2_0, pattern3_0)?; @@ -5646,7 +5837,7 @@ pub fn constructor_atomic_rmw_and( if pattern0_0 == I64 { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2604. + // Rule at src/isa/s390x/inst.isle line 2673. let expr0_0: Type = I64; let expr1_0 = ALUOp::And64; let expr2_0 = constructor_atomic_rmw_impl(ctx, expr0_0, &expr1_0, pattern2_0, pattern3_0)?; @@ -5666,7 +5857,7 @@ pub fn constructor_atomic_rmw_or( if pattern0_0 == I32 { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2607. + // Rule at src/isa/s390x/inst.isle line 2676. let expr0_0: Type = I32; let expr1_0 = ALUOp::Orr32; let expr2_0 = constructor_atomic_rmw_impl(ctx, expr0_0, &expr1_0, pattern2_0, pattern3_0)?; @@ -5675,7 +5866,7 @@ pub fn constructor_atomic_rmw_or( if pattern0_0 == I64 { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2608. + // Rule at src/isa/s390x/inst.isle line 2677. let expr0_0: Type = I64; let expr1_0 = ALUOp::Orr64; let expr2_0 = constructor_atomic_rmw_impl(ctx, expr0_0, &expr1_0, pattern2_0, pattern3_0)?; @@ -5695,7 +5886,7 @@ pub fn constructor_atomic_rmw_xor( if pattern0_0 == I32 { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2611. + // Rule at src/isa/s390x/inst.isle line 2680. let expr0_0: Type = I32; let expr1_0 = ALUOp::Xor32; let expr2_0 = constructor_atomic_rmw_impl(ctx, expr0_0, &expr1_0, pattern2_0, pattern3_0)?; @@ -5704,7 +5895,7 @@ pub fn constructor_atomic_rmw_xor( if pattern0_0 == I64 { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2612. + // Rule at src/isa/s390x/inst.isle line 2681. let expr0_0: Type = I64; let expr1_0 = ALUOp::Xor64; let expr2_0 = constructor_atomic_rmw_impl(ctx, expr0_0, &expr1_0, pattern2_0, pattern3_0)?; @@ -5724,7 +5915,7 @@ pub fn constructor_atomic_rmw_add( if pattern0_0 == I32 { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2615. + // Rule at src/isa/s390x/inst.isle line 2684. let expr0_0: Type = I32; let expr1_0 = ALUOp::Add32; let expr2_0 = constructor_atomic_rmw_impl(ctx, expr0_0, &expr1_0, pattern2_0, pattern3_0)?; @@ -5733,7 +5924,7 @@ pub fn constructor_atomic_rmw_add( if pattern0_0 == I64 { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2616. + // Rule at src/isa/s390x/inst.isle line 2685. let expr0_0: Type = I64; let expr1_0 = ALUOp::Add64; let expr2_0 = constructor_atomic_rmw_impl(ctx, expr0_0, &expr1_0, pattern2_0, pattern3_0)?; @@ -5746,12 +5937,12 @@ pub fn constructor_atomic_rmw_add( pub fn constructor_fpuop2_add(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2622. + // Rule at src/isa/s390x/inst.isle line 2691. let expr0_0 = FPUOp2::Add32; return Some(expr0_0); } if pattern0_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2623. + // Rule at src/isa/s390x/inst.isle line 2692. let expr0_0 = FPUOp2::Add64; return Some(expr0_0); } @@ -5768,7 +5959,7 @@ pub fn constructor_fadd_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2626. + // Rule at src/isa/s390x/inst.isle line 2695. let expr0_0 = constructor_fpuop2_add(ctx, pattern0_0)?; let expr1_0 = constructor_fpu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -5778,12 +5969,12 @@ pub fn constructor_fadd_reg( pub fn constructor_fpuop2_sub(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2632. + // Rule at src/isa/s390x/inst.isle line 2701. let expr0_0 = FPUOp2::Sub32; return Some(expr0_0); } if pattern0_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2633. + // Rule at src/isa/s390x/inst.isle line 2702. let expr0_0 = FPUOp2::Sub64; return Some(expr0_0); } @@ -5800,7 +5991,7 @@ pub fn constructor_fsub_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2636. + // Rule at src/isa/s390x/inst.isle line 2705. let expr0_0 = constructor_fpuop2_sub(ctx, pattern0_0)?; let expr1_0 = constructor_fpu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -5810,12 +6001,12 @@ pub fn constructor_fsub_reg( pub fn constructor_fpuop2_mul(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2642. + // Rule at src/isa/s390x/inst.isle line 2711. let expr0_0 = FPUOp2::Mul32; return Some(expr0_0); } if pattern0_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2643. + // Rule at src/isa/s390x/inst.isle line 2712. let expr0_0 = FPUOp2::Mul64; return Some(expr0_0); } @@ -5832,7 +6023,7 @@ pub fn constructor_fmul_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2646. + // Rule at src/isa/s390x/inst.isle line 2715. let expr0_0 = constructor_fpuop2_mul(ctx, pattern0_0)?; let expr1_0 = constructor_fpu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -5842,12 +6033,12 @@ pub fn constructor_fmul_reg( pub fn constructor_fpuop2_div(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2652. + // Rule at src/isa/s390x/inst.isle line 2721. let expr0_0 = FPUOp2::Div32; return Some(expr0_0); } if pattern0_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2653. + // Rule at src/isa/s390x/inst.isle line 2722. let expr0_0 = FPUOp2::Div64; return Some(expr0_0); } @@ -5864,7 +6055,7 @@ pub fn constructor_fdiv_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2656. + // Rule at src/isa/s390x/inst.isle line 2725. let expr0_0 = constructor_fpuop2_div(ctx, pattern0_0)?; let expr1_0 = constructor_fpu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -5874,12 +6065,12 @@ pub fn constructor_fdiv_reg( pub fn constructor_fpuop2_min(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2662. + // Rule at src/isa/s390x/inst.isle line 2731. let expr0_0 = FPUOp2::Min32; return Some(expr0_0); } if pattern0_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2663. + // Rule at src/isa/s390x/inst.isle line 2732. let expr0_0 = FPUOp2::Min64; return Some(expr0_0); } @@ -5896,7 +6087,7 @@ pub fn constructor_fmin_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2666. + // Rule at src/isa/s390x/inst.isle line 2735. let expr0_0 = constructor_fpuop2_min(ctx, pattern0_0)?; let expr1_0 = constructor_fpuvec_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -5906,12 +6097,12 @@ pub fn constructor_fmin_reg( pub fn constructor_fpuop2_max(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2672. + // Rule at src/isa/s390x/inst.isle line 2741. let expr0_0 = FPUOp2::Max32; return Some(expr0_0); } if pattern0_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2673. + // Rule at src/isa/s390x/inst.isle line 2742. let expr0_0 = FPUOp2::Max64; return Some(expr0_0); } @@ -5928,7 +6119,7 @@ pub fn constructor_fmax_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2676. + // Rule at src/isa/s390x/inst.isle line 2745. let expr0_0 = constructor_fpuop2_max(ctx, pattern0_0)?; let expr1_0 = constructor_fpuvec_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -5938,12 +6129,12 @@ pub fn constructor_fmax_reg( pub fn constructor_fpuop3_fma(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2682. + // Rule at src/isa/s390x/inst.isle line 2751. let expr0_0 = FPUOp3::MAdd32; return Some(expr0_0); } if pattern0_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2683. + // Rule at src/isa/s390x/inst.isle line 2752. let expr0_0 = FPUOp3::MAdd64; return Some(expr0_0); } @@ -5962,7 +6153,7 @@ pub fn constructor_fma_reg( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/s390x/inst.isle line 2686. + // Rule at src/isa/s390x/inst.isle line 2755. let expr0_0 = constructor_fpuop3_fma(ctx, pattern0_0)?; let expr1_0 = constructor_fpu_rrrr( ctx, pattern0_0, &expr0_0, pattern3_0, pattern1_0, pattern2_0, @@ -5974,12 +6165,12 @@ pub fn constructor_fma_reg( pub fn constructor_fpuop1_sqrt(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2692. + // Rule at src/isa/s390x/inst.isle line 2761. let expr0_0 = FPUOp1::Sqrt32; return Some(expr0_0); } if pattern0_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2693. + // Rule at src/isa/s390x/inst.isle line 2762. let expr0_0 = FPUOp1::Sqrt64; return Some(expr0_0); } @@ -5990,7 +6181,7 @@ pub fn constructor_fpuop1_sqrt(ctx: &mut C, arg0: Type) -> Option(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2696. + // Rule at src/isa/s390x/inst.isle line 2765. let expr0_0 = constructor_fpuop1_sqrt(ctx, pattern0_0)?; let expr1_0 = constructor_fpu_rr(ctx, pattern0_0, &expr0_0, pattern1_0)?; return Some(expr1_0); @@ -6000,12 +6191,12 @@ pub fn constructor_sqrt_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> O pub fn constructor_fpuop1_neg(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2702. + // Rule at src/isa/s390x/inst.isle line 2771. let expr0_0 = FPUOp1::Neg32; return Some(expr0_0); } if pattern0_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2703. + // Rule at src/isa/s390x/inst.isle line 2772. let expr0_0 = FPUOp1::Neg64; return Some(expr0_0); } @@ -6016,7 +6207,7 @@ pub fn constructor_fpuop1_neg(ctx: &mut C, arg0: Type) -> Option(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2706. + // Rule at src/isa/s390x/inst.isle line 2775. let expr0_0 = constructor_fpuop1_neg(ctx, pattern0_0)?; let expr1_0 = constructor_fpu_rr(ctx, pattern0_0, &expr0_0, pattern1_0)?; return Some(expr1_0); @@ -6026,12 +6217,12 @@ pub fn constructor_fneg_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> O pub fn constructor_fpuop1_abs(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2712. + // Rule at src/isa/s390x/inst.isle line 2781. let expr0_0 = FPUOp1::Abs32; return Some(expr0_0); } if pattern0_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2713. + // Rule at src/isa/s390x/inst.isle line 2782. let expr0_0 = FPUOp1::Abs64; return Some(expr0_0); } @@ -6042,7 +6233,7 @@ pub fn constructor_fpuop1_abs(ctx: &mut C, arg0: Type) -> Option(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2716. + // Rule at src/isa/s390x/inst.isle line 2785. let expr0_0 = constructor_fpuop1_abs(ctx, pattern0_0)?; let expr1_0 = constructor_fpu_rr(ctx, pattern0_0, &expr0_0, pattern1_0)?; return Some(expr1_0); @@ -6052,12 +6243,12 @@ pub fn constructor_fabs_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> O pub fn constructor_fpuroundmode_ceil(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2722. + // Rule at src/isa/s390x/inst.isle line 2791. let expr0_0 = FpuRoundMode::Plus32; return Some(expr0_0); } if pattern0_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2723. + // Rule at src/isa/s390x/inst.isle line 2792. let expr0_0 = FpuRoundMode::Plus64; return Some(expr0_0); } @@ -6068,7 +6259,7 @@ pub fn constructor_fpuroundmode_ceil(ctx: &mut C, arg0: Type) -> Opt pub fn constructor_ceil_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2726. + // Rule at src/isa/s390x/inst.isle line 2795. let expr0_0 = constructor_fpuroundmode_ceil(ctx, pattern0_0)?; let expr1_0 = constructor_fpu_round(ctx, pattern0_0, &expr0_0, pattern1_0)?; return Some(expr1_0); @@ -6078,12 +6269,12 @@ pub fn constructor_ceil_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> O pub fn constructor_fpuroundmode_floor(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2732. + // Rule at src/isa/s390x/inst.isle line 2801. let expr0_0 = FpuRoundMode::Minus32; return Some(expr0_0); } if pattern0_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2733. + // Rule at src/isa/s390x/inst.isle line 2802. let expr0_0 = FpuRoundMode::Minus64; return Some(expr0_0); } @@ -6094,7 +6285,7 @@ pub fn constructor_fpuroundmode_floor(ctx: &mut C, arg0: Type) -> Op pub fn constructor_floor_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2736. + // Rule at src/isa/s390x/inst.isle line 2805. let expr0_0 = constructor_fpuroundmode_floor(ctx, pattern0_0)?; let expr1_0 = constructor_fpu_round(ctx, pattern0_0, &expr0_0, pattern1_0)?; return Some(expr1_0); @@ -6104,12 +6295,12 @@ pub fn constructor_floor_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> pub fn constructor_fpuroundmode_trunc(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2742. + // Rule at src/isa/s390x/inst.isle line 2811. let expr0_0 = FpuRoundMode::Zero32; return Some(expr0_0); } if pattern0_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2743. + // Rule at src/isa/s390x/inst.isle line 2812. let expr0_0 = FpuRoundMode::Zero64; return Some(expr0_0); } @@ -6120,7 +6311,7 @@ pub fn constructor_fpuroundmode_trunc(ctx: &mut C, arg0: Type) -> Op pub fn constructor_trunc_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2746. + // Rule at src/isa/s390x/inst.isle line 2815. let expr0_0 = constructor_fpuroundmode_trunc(ctx, pattern0_0)?; let expr1_0 = constructor_fpu_round(ctx, pattern0_0, &expr0_0, pattern1_0)?; return Some(expr1_0); @@ -6133,12 +6324,12 @@ pub fn constructor_fpuroundmode_nearest( ) -> Option { let pattern0_0 = arg0; if pattern0_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2752. + // Rule at src/isa/s390x/inst.isle line 2821. let expr0_0 = FpuRoundMode::Nearest32; return Some(expr0_0); } if pattern0_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2753. + // Rule at src/isa/s390x/inst.isle line 2822. let expr0_0 = FpuRoundMode::Nearest64; return Some(expr0_0); } @@ -6149,7 +6340,7 @@ pub fn constructor_fpuroundmode_nearest( pub fn constructor_nearest_reg(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/s390x/inst.isle line 2756. + // Rule at src/isa/s390x/inst.isle line 2825. let expr0_0 = constructor_fpuroundmode_nearest(ctx, pattern0_0)?; let expr1_0 = constructor_fpu_round(ctx, pattern0_0, &expr0_0, pattern1_0)?; return Some(expr1_0); @@ -6165,7 +6356,7 @@ pub fn constructor_fpuop1_promote( if pattern0_0 == F64 { let pattern2_0 = arg1; if pattern2_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2762. + // Rule at src/isa/s390x/inst.isle line 2831. let expr0_0 = FPUOp1::Cvt32To64; return Some(expr0_0); } @@ -6183,7 +6374,7 @@ pub fn constructor_fpromote_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2765. + // Rule at src/isa/s390x/inst.isle line 2834. let expr0_0 = constructor_fpuop1_promote(ctx, pattern0_0, pattern1_0)?; let expr1_0 = constructor_fpu_rr(ctx, pattern0_0, &expr0_0, pattern2_0)?; return Some(expr1_0); @@ -6199,7 +6390,7 @@ pub fn constructor_fpuop1_demote( if pattern0_0 == F32 { let pattern2_0 = arg1; if pattern2_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2772. + // Rule at src/isa/s390x/inst.isle line 2841. let expr0_0 = FPUOp1::Cvt64To32; return Some(expr0_0); } @@ -6217,7 +6408,7 @@ pub fn constructor_fdemote_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2775. + // Rule at src/isa/s390x/inst.isle line 2844. let expr0_0 = constructor_fpuop1_demote(ctx, pattern0_0, pattern1_0)?; let expr1_0 = constructor_fpu_rr(ctx, pattern0_0, &expr0_0, pattern2_0)?; return Some(expr1_0); @@ -6233,12 +6424,12 @@ pub fn constructor_uint_to_fpu_op( if pattern0_0 == F32 { let pattern2_0 = arg1; if pattern2_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2782. + // Rule at src/isa/s390x/inst.isle line 2851. let expr0_0 = IntToFpuOp::U32ToF32; return Some(expr0_0); } if pattern2_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2784. + // Rule at src/isa/s390x/inst.isle line 2853. let expr0_0 = IntToFpuOp::U64ToF32; return Some(expr0_0); } @@ -6246,12 +6437,12 @@ pub fn constructor_uint_to_fpu_op( if pattern0_0 == F64 { let pattern2_0 = arg1; if pattern2_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2783. + // Rule at src/isa/s390x/inst.isle line 2852. let expr0_0 = IntToFpuOp::U32ToF64; return Some(expr0_0); } if pattern2_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2785. + // Rule at src/isa/s390x/inst.isle line 2854. let expr0_0 = IntToFpuOp::U64ToF64; return Some(expr0_0); } @@ -6269,7 +6460,7 @@ pub fn constructor_fcvt_from_uint_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2788. + // Rule at src/isa/s390x/inst.isle line 2857. let expr0_0 = constructor_uint_to_fpu_op(ctx, pattern0_0, pattern1_0)?; let expr1_0 = constructor_int_to_fpu(ctx, pattern0_0, &expr0_0, pattern2_0)?; return Some(expr1_0); @@ -6285,12 +6476,12 @@ pub fn constructor_sint_to_fpu_op( if pattern0_0 == F32 { let pattern2_0 = arg1; if pattern2_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2795. + // Rule at src/isa/s390x/inst.isle line 2864. let expr0_0 = IntToFpuOp::I32ToF32; return Some(expr0_0); } if pattern2_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2797. + // Rule at src/isa/s390x/inst.isle line 2866. let expr0_0 = IntToFpuOp::I64ToF32; return Some(expr0_0); } @@ -6298,12 +6489,12 @@ pub fn constructor_sint_to_fpu_op( if pattern0_0 == F64 { let pattern2_0 = arg1; if pattern2_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2796. + // Rule at src/isa/s390x/inst.isle line 2865. let expr0_0 = IntToFpuOp::I32ToF64; return Some(expr0_0); } if pattern2_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2798. + // Rule at src/isa/s390x/inst.isle line 2867. let expr0_0 = IntToFpuOp::I64ToF64; return Some(expr0_0); } @@ -6321,7 +6512,7 @@ pub fn constructor_fcvt_from_sint_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2801. + // Rule at src/isa/s390x/inst.isle line 2870. let expr0_0 = constructor_sint_to_fpu_op(ctx, pattern0_0, pattern1_0)?; let expr1_0 = constructor_int_to_fpu(ctx, pattern0_0, &expr0_0, pattern2_0)?; return Some(expr1_0); @@ -6337,12 +6528,12 @@ pub fn constructor_fpu_to_uint_op( if pattern0_0 == I32 { let pattern2_0 = arg1; if pattern2_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2808. + // Rule at src/isa/s390x/inst.isle line 2877. let expr0_0 = FpuToIntOp::F32ToU32; return Some(expr0_0); } if pattern2_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2809. + // Rule at src/isa/s390x/inst.isle line 2878. let expr0_0 = FpuToIntOp::F64ToU32; return Some(expr0_0); } @@ -6350,12 +6541,12 @@ pub fn constructor_fpu_to_uint_op( if pattern0_0 == I64 { let pattern2_0 = arg1; if pattern2_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2810. + // Rule at src/isa/s390x/inst.isle line 2879. let expr0_0 = FpuToIntOp::F32ToU64; return Some(expr0_0); } if pattern2_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2811. + // Rule at src/isa/s390x/inst.isle line 2880. let expr0_0 = FpuToIntOp::F64ToU64; return Some(expr0_0); } @@ -6373,7 +6564,7 @@ pub fn constructor_fcvt_to_uint_reg_with_flags( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2814. + // Rule at src/isa/s390x/inst.isle line 2883. let expr0_0 = constructor_fpu_to_uint_op(ctx, pattern0_0, pattern1_0)?; let expr1_0 = constructor_fpu_to_int(ctx, pattern0_0, &expr0_0, pattern2_0)?; return Some(expr1_0); @@ -6389,7 +6580,7 @@ pub fn constructor_fcvt_to_uint_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2818. + // Rule at src/isa/s390x/inst.isle line 2887. let expr0_0 = constructor_fcvt_to_uint_reg_with_flags(ctx, pattern0_0, pattern1_0, pattern2_0)?; let expr1_0 = constructor_drop_flags(ctx, &expr0_0)?; return Some(expr1_0); @@ -6405,12 +6596,12 @@ pub fn constructor_fpu_to_sint_op( if pattern0_0 == I32 { let pattern2_0 = arg1; if pattern2_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2825. + // Rule at src/isa/s390x/inst.isle line 2894. let expr0_0 = FpuToIntOp::F32ToI32; return Some(expr0_0); } if pattern2_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2826. + // Rule at src/isa/s390x/inst.isle line 2895. let expr0_0 = FpuToIntOp::F64ToI32; return Some(expr0_0); } @@ -6418,12 +6609,12 @@ pub fn constructor_fpu_to_sint_op( if pattern0_0 == I64 { let pattern2_0 = arg1; if pattern2_0 == F32 { - // Rule at src/isa/s390x/inst.isle line 2827. + // Rule at src/isa/s390x/inst.isle line 2896. let expr0_0 = FpuToIntOp::F32ToI64; return Some(expr0_0); } if pattern2_0 == F64 { - // Rule at src/isa/s390x/inst.isle line 2828. + // Rule at src/isa/s390x/inst.isle line 2897. let expr0_0 = FpuToIntOp::F64ToI64; return Some(expr0_0); } @@ -6441,7 +6632,7 @@ pub fn constructor_fcvt_to_sint_reg_with_flags( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2831. + // Rule at src/isa/s390x/inst.isle line 2900. let expr0_0 = constructor_fpu_to_sint_op(ctx, pattern0_0, pattern1_0)?; let expr1_0 = constructor_fpu_to_int(ctx, pattern0_0, &expr0_0, pattern2_0)?; return Some(expr1_0); @@ -6457,7 +6648,7 @@ pub fn constructor_fcvt_to_sint_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2835. + // Rule at src/isa/s390x/inst.isle line 2904. let expr0_0 = constructor_fcvt_to_sint_reg_with_flags(ctx, pattern0_0, pattern1_0, pattern2_0)?; let expr1_0 = constructor_drop_flags(ctx, &expr0_0)?; return Some(expr1_0); @@ -6467,12 +6658,12 @@ pub fn constructor_fcvt_to_sint_reg( pub fn constructor_cmpop_cmps(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2842. + // Rule at src/isa/s390x/inst.isle line 2911. let expr0_0 = CmpOp::CmpS32; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2843. + // Rule at src/isa/s390x/inst.isle line 2912. let expr0_0 = CmpOp::CmpS64; return Some(expr0_0); } @@ -6483,12 +6674,12 @@ pub fn constructor_cmpop_cmps(ctx: &mut C, arg0: Type) -> Option(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2846. + // Rule at src/isa/s390x/inst.isle line 2915. let expr0_0 = CmpOp::CmpS32Ext16; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2847. + // Rule at src/isa/s390x/inst.isle line 2916. let expr0_0 = CmpOp::CmpS64Ext16; return Some(expr0_0); } @@ -6499,7 +6690,7 @@ pub fn constructor_cmpop_cmps_sext16(ctx: &mut C, arg0: Type) -> Opt pub fn constructor_cmpop_cmps_sext32(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2850. + // Rule at src/isa/s390x/inst.isle line 2919. let expr0_0 = CmpOp::CmpS64Ext32; return Some(expr0_0); } @@ -6516,7 +6707,7 @@ pub fn constructor_icmps_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2853. + // Rule at src/isa/s390x/inst.isle line 2922. let expr0_0 = constructor_cmpop_cmps(ctx, pattern0_0)?; let expr1_0 = constructor_cmp_rr(ctx, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -6532,7 +6723,7 @@ pub fn constructor_icmps_reg_sext32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2856. + // Rule at src/isa/s390x/inst.isle line 2925. let expr0_0 = constructor_cmpop_cmps_sext32(ctx, pattern0_0)?; let expr1_0 = constructor_cmp_rr(ctx, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -6548,7 +6739,7 @@ pub fn constructor_icmps_simm16( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2859. + // Rule at src/isa/s390x/inst.isle line 2928. let expr0_0 = constructor_cmpop_cmps(ctx, pattern0_0)?; let expr1_0 = constructor_cmp_rsimm16(ctx, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -6564,7 +6755,7 @@ pub fn constructor_icmps_simm32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2862. + // Rule at src/isa/s390x/inst.isle line 2931. let expr0_0 = constructor_cmpop_cmps(ctx, pattern0_0)?; let expr1_0 = constructor_cmp_rsimm32(ctx, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -6580,7 +6771,7 @@ pub fn constructor_icmps_mem( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2865. + // Rule at src/isa/s390x/inst.isle line 2934. let expr0_0 = constructor_cmpop_cmps(ctx, pattern0_0)?; let expr1_0 = constructor_cmp_rx(ctx, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -6596,7 +6787,7 @@ pub fn constructor_icmps_mem_sext16( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2868. + // Rule at src/isa/s390x/inst.isle line 2937. let expr0_0 = constructor_cmpop_cmps_sext16(ctx, pattern0_0)?; let expr1_0 = constructor_cmp_rx(ctx, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -6612,7 +6803,7 @@ pub fn constructor_icmps_mem_sext32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2871. + // Rule at src/isa/s390x/inst.isle line 2940. let expr0_0 = constructor_cmpop_cmps_sext32(ctx, pattern0_0)?; let expr1_0 = constructor_cmp_rx(ctx, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -6622,12 +6813,12 @@ pub fn constructor_icmps_mem_sext32( pub fn constructor_cmpop_cmpu(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2877. + // Rule at src/isa/s390x/inst.isle line 2946. let expr0_0 = CmpOp::CmpL32; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2878. + // Rule at src/isa/s390x/inst.isle line 2947. let expr0_0 = CmpOp::CmpL64; return Some(expr0_0); } @@ -6638,12 +6829,12 @@ pub fn constructor_cmpop_cmpu(ctx: &mut C, arg0: Type) -> Option(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I32 { - // Rule at src/isa/s390x/inst.isle line 2881. + // Rule at src/isa/s390x/inst.isle line 2950. let expr0_0 = CmpOp::CmpL32Ext16; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2882. + // Rule at src/isa/s390x/inst.isle line 2951. let expr0_0 = CmpOp::CmpL64Ext16; return Some(expr0_0); } @@ -6654,7 +6845,7 @@ pub fn constructor_cmpop_cmpu_zext16(ctx: &mut C, arg0: Type) -> Opt pub fn constructor_cmpop_cmpu_zext32(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I64 { - // Rule at src/isa/s390x/inst.isle line 2885. + // Rule at src/isa/s390x/inst.isle line 2954. let expr0_0 = CmpOp::CmpL64Ext32; return Some(expr0_0); } @@ -6671,7 +6862,7 @@ pub fn constructor_icmpu_reg( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2888. + // Rule at src/isa/s390x/inst.isle line 2957. let expr0_0 = constructor_cmpop_cmpu(ctx, pattern0_0)?; let expr1_0 = constructor_cmp_rr(ctx, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -6687,7 +6878,7 @@ pub fn constructor_icmpu_reg_zext32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2891. + // Rule at src/isa/s390x/inst.isle line 2960. let expr0_0 = constructor_cmpop_cmpu_zext32(ctx, pattern0_0)?; let expr1_0 = constructor_cmp_rr(ctx, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -6703,7 +6894,7 @@ pub fn constructor_icmpu_uimm32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2894. + // Rule at src/isa/s390x/inst.isle line 2963. let expr0_0 = constructor_cmpop_cmpu(ctx, pattern0_0)?; let expr1_0 = constructor_cmp_ruimm32(ctx, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -6719,7 +6910,7 @@ pub fn constructor_icmpu_mem( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2897. + // Rule at src/isa/s390x/inst.isle line 2966. let expr0_0 = constructor_cmpop_cmpu(ctx, pattern0_0)?; let expr1_0 = constructor_cmp_rx(ctx, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -6735,7 +6926,7 @@ pub fn constructor_icmpu_mem_zext16( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2900. + // Rule at src/isa/s390x/inst.isle line 2969. let expr0_0 = constructor_cmpop_cmpu_zext16(ctx, pattern0_0)?; let expr1_0 = constructor_cmp_rx(ctx, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -6751,7 +6942,7 @@ pub fn constructor_icmpu_mem_zext32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2903. + // Rule at src/isa/s390x/inst.isle line 2972. let expr0_0 = constructor_cmpop_cmpu_zext32(ctx, pattern0_0)?; let expr1_0 = constructor_cmp_rx(ctx, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -6768,14 +6959,14 @@ pub fn constructor_fcmp_reg( if pattern0_0 == F32 { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2909. + // Rule at src/isa/s390x/inst.isle line 2978. let expr0_0 = constructor_fpu_cmp32(ctx, pattern2_0, pattern3_0)?; return Some(expr0_0); } if pattern0_0 == F64 { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/inst.isle line 2910. + // Rule at src/isa/s390x/inst.isle line 2979. let expr0_0 = constructor_fpu_cmp64(ctx, pattern2_0, pattern3_0)?; return Some(expr0_0); } @@ -6791,14 +6982,20 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { match &pattern2_0 { + &Opcode::Debugtrap => { + // Rule at src/isa/s390x/lower.isle line 1892. + let expr0_0 = constructor_debugtrap_impl(ctx)?; + let expr1_0 = constructor_value_regs_none(ctx, &expr0_0)?; + return Some(expr1_0); + } &Opcode::Nop => { - // Rule at src/isa/s390x/lower.isle line 42. + // Rule at src/isa/s390x/lower.isle line 47. let expr0_0 = C::invalid_reg(ctx); let expr1_0 = C::value_reg(ctx, expr0_0); return Some(expr1_0); } &Opcode::Fence => { - // Rule at src/isa/s390x/lower.isle line 1600. + // Rule at src/isa/s390x/lower.isle line 1605. let expr0_0 = constructor_fence_impl(ctx)?; let expr1_0 = constructor_value_regs_none(ctx, &expr0_0)?; return Some(expr1_0); @@ -6813,7 +7010,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::F32const = &pattern2_0 { let pattern4_0 = C::u64_from_ieee32(ctx, pattern2_1); - // Rule at src/isa/s390x/lower.isle line 24. + // Rule at src/isa/s390x/lower.isle line 29. let expr0_0: Type = F32; let expr1_0 = constructor_imm(ctx, expr0_0, pattern4_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); @@ -6876,13 +7073,33 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::F64const = &pattern2_0 { let pattern4_0 = C::u64_from_ieee64(ctx, pattern2_1); - // Rule at src/isa/s390x/lower.isle line 30. + // Rule at src/isa/s390x/lower.isle line 35. let expr0_0: Type = F64; let expr1_0 = constructor_imm(ctx, expr0_0, pattern4_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); return Some(expr2_0); } } + &InstructionData::Trap { + opcode: ref pattern2_0, + code: ref pattern2_1, + } => { + match &pattern2_0 { + &Opcode::Trap => { + // Rule at src/isa/s390x/lower.isle line 1862. + let expr0_0 = constructor_trap_impl(ctx, &pattern2_1)?; + let expr1_0 = constructor_safepoint(ctx, &expr0_0)?; + return Some(expr1_0); + } + &Opcode::ResumableTrap => { + // Rule at src/isa/s390x/lower.isle line 1868. + let expr0_0 = constructor_trap_impl(ctx, &pattern2_1)?; + let expr1_0 = constructor_safepoint(ctx, &expr0_0)?; + return Some(expr1_0); + } + _ => {} + } + } &InstructionData::StoreNoOffset { opcode: ref pattern2_0, args: ref pattern2_1, @@ -6892,7 +7109,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { let (pattern4_0, pattern4_1) = C::unpack_value_array_2(ctx, &pattern2_1); - // Rule at src/isa/s390x/lower.isle line 1412. + // Rule at src/isa/s390x/lower.isle line 1417. let expr0_0 = constructor_istore8_impl( ctx, pattern2_2, pattern4_0, pattern4_1, pattern2_3, )?; @@ -7065,7 +7282,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern4_0, pattern4_1) = C::unpack_value_array_2(ctx, &pattern2_1); - // Rule at src/isa/s390x/lower.isle line 1430. + // Rule at src/isa/s390x/lower.isle line 1435. let expr0_0 = constructor_istore16_impl( ctx, pattern2_2, pattern4_0, pattern4_1, pattern2_3, )?; @@ -7074,7 +7291,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern4_0, pattern4_1) = C::unpack_value_array_2(ctx, &pattern2_1); - // Rule at src/isa/s390x/lower.isle line 1456. + // Rule at src/isa/s390x/lower.isle line 1461. let expr0_0 = constructor_istore32_impl( ctx, pattern2_2, pattern4_0, pattern4_1, pattern2_3, )?; @@ -7090,19 +7307,19 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { match &pattern2_0 { &Opcode::Copy => { - // Rule at src/isa/s390x/lower.isle line 48. + // Rule at src/isa/s390x/lower.isle line 53. let expr0_0 = C::put_in_reg(ctx, pattern2_1); let expr1_0 = C::value_reg(ctx, expr0_0); return Some(expr1_0); } &Opcode::Breduce => { - // Rule at src/isa/s390x/lower.isle line 747. + // Rule at src/isa/s390x/lower.isle line 752. let expr0_0 = C::put_in_reg(ctx, pattern2_1); let expr1_0 = C::value_reg(ctx, expr0_0); return Some(expr1_0); } &Opcode::Ireduce => { - // Rule at src/isa/s390x/lower.isle line 591. + // Rule at src/isa/s390x/lower.isle line 596. let expr0_0 = C::put_in_reg(ctx, pattern2_1); let expr1_0 = C::value_reg(ctx, expr0_0); return Some(expr1_0); @@ -7110,6 +7327,87 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option {} } } + &InstructionData::IntCondTrap { + opcode: ref pattern2_0, + arg: pattern2_1, + cond: ref pattern2_2, + code: ref pattern2_3, + } => { + if let &Opcode::Trapif = &pattern2_0 { + if let Some(pattern4_0) = C::def_inst(ctx, pattern2_1) { + let pattern5_0 = C::inst_data(ctx, pattern4_0); + if let &InstructionData::Binary { + opcode: ref pattern6_0, + args: ref pattern6_1, + } = &pattern5_0 + { + match &pattern6_0 { + &Opcode::Ifcmp => { + let (pattern8_0, pattern8_1) = + C::unpack_value_array_2(ctx, &pattern6_1); + // Rule at src/isa/s390x/lower.isle line 1904. + let expr0_0: bool = false; + let expr1_0 = constructor_icmp_val( + ctx, + expr0_0, + &pattern2_2, + pattern8_0, + pattern8_1, + )?; + let expr2_0 = constructor_trap_if_bool(ctx, &expr1_0, &pattern2_3)?; + let expr3_0 = constructor_safepoint(ctx, &expr2_0)?; + return Some(expr3_0); + } + &Opcode::IaddIfcout => { + let (pattern8_0, pattern8_1) = + C::unpack_value_array_2(ctx, &pattern6_1); + if let &IntCC::UnsignedGreaterThan = &pattern2_2 { + // Rule at src/isa/s390x/lower.isle line 1929. + let expr0_0: u8 = 3; + let expr1_0 = C::mask_as_cond(ctx, expr0_0); + let expr2_0 = + constructor_trap_if_impl(ctx, &expr1_0, &pattern2_3)?; + let expr3_0 = constructor_value_regs_none(ctx, &expr2_0)?; + return Some(expr3_0); + } + } + _ => {} + } + } + } + } + } + &InstructionData::CondTrap { + opcode: ref pattern2_0, + arg: pattern2_1, + code: ref pattern2_2, + } => { + match &pattern2_0 { + &Opcode::Trapz => { + // Rule at src/isa/s390x/lower.isle line 1874. + let expr0_0 = constructor_value_nonzero(ctx, pattern2_1)?; + let expr1_0 = constructor_invert_bool(ctx, &expr0_0)?; + let expr2_0 = constructor_trap_if_bool(ctx, &expr1_0, &pattern2_2)?; + let expr3_0 = constructor_safepoint(ctx, &expr2_0)?; + return Some(expr3_0); + } + &Opcode::Trapnz => { + // Rule at src/isa/s390x/lower.isle line 1880. + let expr0_0 = constructor_value_nonzero(ctx, pattern2_1)?; + let expr1_0 = constructor_trap_if_bool(ctx, &expr0_0, &pattern2_2)?; + let expr2_0 = constructor_safepoint(ctx, &expr1_0)?; + return Some(expr2_0); + } + &Opcode::ResumableTrapnz => { + // Rule at src/isa/s390x/lower.isle line 1886. + let expr0_0 = constructor_value_nonzero(ctx, pattern2_1)?; + let expr1_0 = constructor_trap_if_bool(ctx, &expr0_0, &pattern2_2)?; + let expr2_0 = constructor_safepoint(ctx, &expr1_0)?; + return Some(expr2_0); + } + _ => {} + } + } _ => {} } if let Some(pattern1_0) = C::first_result(ctx, pattern0_0) { @@ -7125,7 +7423,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let pattern7_0 = C::value_type(ctx, pattern5_1); if pattern7_0 == R64 { - // Rule at src/isa/s390x/lower.isle line 1735. + // Rule at src/isa/s390x/lower.isle line 1740. let expr0_0: Type = B1; let expr1_0: Type = I64; let expr2_0 = C::put_in_reg(ctx, pattern5_1); @@ -7142,7 +7440,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let pattern7_0 = C::value_type(ctx, pattern5_1); if pattern7_0 == R64 { - // Rule at src/isa/s390x/lower.isle line 1741. + // Rule at src/isa/s390x/lower.isle line 1746. let expr0_0: Type = B1; let expr1_0: Type = I64; let expr2_0 = C::put_in_reg(ctx, pattern5_1); @@ -7168,7 +7466,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Popcnt = &pattern5_0 { - // Rule at src/isa/s390x/lower.isle line 879. + // Rule at src/isa/s390x/lower.isle line 884. let expr0_0 = C::put_in_reg(ctx, pattern5_1); let expr1_0 = constructor_popcnt_byte(ctx, expr0_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); @@ -7181,7 +7479,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::AtomicLoad = &pattern5_0 { - // Rule at src/isa/s390x/lower.isle line 1544. + // Rule at src/isa/s390x/lower.isle line 1549. let expr0_0: Type = I8; let expr1_0 = C::zero_offset(ctx); let expr2_0 = @@ -7198,7 +7496,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Load = &pattern5_0 { - // Rule at src/isa/s390x/lower.isle line 1181. + // Rule at src/isa/s390x/lower.isle line 1186. let expr0_0: Type = I8; let expr1_0 = constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?; @@ -7220,7 +7518,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::AtomicLoad = &pattern5_0 { if let Some(()) = C::littleendian(ctx, pattern5_2) { - // Rule at src/isa/s390x/lower.isle line 1552. + // Rule at src/isa/s390x/lower.isle line 1557. let expr0_0 = C::zero_offset(ctx); let expr1_0 = constructor_lower_address(ctx, pattern5_2, pattern5_1, expr0_0)?; @@ -7229,7 +7527,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Load = &pattern5_0 { if let Some(()) = C::littleendian(ctx, pattern5_2) { - // Rule at src/isa/s390x/lower.isle line 1189. + // Rule at src/isa/s390x/lower.isle line 1194. let expr0_0 = constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?; let expr1_0 = constructor_loadrev16(ctx, &expr0_0)?; @@ -7256,7 +7554,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/s390x/lower.isle line 247. + // Rule at src/isa/s390x/lower.isle line 252. let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?; let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_1)?; let expr2_0: Type = I64; @@ -7294,7 +7592,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/s390x/lower.isle line 269. + // Rule at src/isa/s390x/lower.isle line 274. let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?; let expr1_0 = constructor_put_in_reg_sext64(ctx, pattern7_1)?; let expr2_0: Type = I64; @@ -7317,7 +7615,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::AtomicLoad = &pattern5_0 { if let Some(()) = C::littleendian(ctx, pattern5_2) { - // Rule at src/isa/s390x/lower.isle line 1560. + // Rule at src/isa/s390x/lower.isle line 1565. let expr0_0 = C::zero_offset(ctx); let expr1_0 = constructor_lower_address(ctx, pattern5_2, pattern5_1, expr0_0)?; @@ -7364,7 +7662,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Load = &pattern5_0 { if let Some(()) = C::littleendian(ctx, pattern5_2) { - // Rule at src/isa/s390x/lower.isle line 1197. + // Rule at src/isa/s390x/lower.isle line 1202. let expr0_0 = constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?; let expr1_0 = constructor_loadrev32(ctx, &expr0_0)?; @@ -7390,7 +7688,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/s390x/lower.isle line 254. + // Rule at src/isa/s390x/lower.isle line 259. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = C::put_in_reg(ctx, pattern7_1); let expr2_0 = constructor_umul_wide(ctx, expr0_0, expr1_0)?; @@ -7426,7 +7724,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/s390x/lower.isle line 276. + // Rule at src/isa/s390x/lower.isle line 281. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = C::put_in_reg(ctx, pattern7_1); let expr2_0 = constructor_smul_wide(ctx, expr0_0, expr1_0)?; @@ -7448,7 +7746,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::AtomicLoad = &pattern5_0 { if let Some(()) = C::littleendian(ctx, pattern5_2) { - // Rule at src/isa/s390x/lower.isle line 1568. + // Rule at src/isa/s390x/lower.isle line 1573. let expr0_0 = C::zero_offset(ctx); let expr1_0 = constructor_lower_address(ctx, pattern5_2, pattern5_1, expr0_0)?; @@ -7492,7 +7790,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Load = &pattern5_0 { if let Some(()) = C::littleendian(ctx, pattern5_2) { - // Rule at src/isa/s390x/lower.isle line 1205. + // Rule at src/isa/s390x/lower.isle line 1210. let expr0_0 = constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?; let expr1_0 = constructor_loadrev64(ctx, &expr0_0)?; @@ -7518,7 +7816,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Load = &pattern5_0 { if let Some(()) = C::bigendian(ctx, pattern5_2) { - // Rule at src/isa/s390x/lower.isle line 1217. + // Rule at src/isa/s390x/lower.isle line 1222. let expr0_0 = constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?; let expr1_0 = constructor_fpu_load32(ctx, &expr0_0)?; @@ -7610,7 +7908,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Load = &pattern5_0 { if let Some(()) = C::bigendian(ctx, pattern5_2) { - // Rule at src/isa/s390x/lower.isle line 1232. + // Rule at src/isa/s390x/lower.isle line 1237. let expr0_0 = constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?; let expr1_0 = constructor_fpu_load64(ctx, &expr0_0)?; @@ -7644,7 +7942,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Null = &pattern4_0 { - // Rule at src/isa/s390x/lower.isle line 36. + // Rule at src/isa/s390x/lower.isle line 41. let expr0_0: u64 = 0; let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); @@ -7657,7 +7955,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Iconst = &pattern4_0 { let pattern6_0 = C::u64_from_imm64(ctx, pattern4_1); - // Rule at src/isa/s390x/lower.isle line 10. + // Rule at src/isa/s390x/lower.isle line 15. let expr0_0 = constructor_imm(ctx, pattern2_0, pattern6_0)?; let expr1_0 = C::value_reg(ctx, expr0_0); return Some(expr1_0); @@ -7669,7 +7967,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::StackAddr = &pattern4_0 { - // Rule at src/isa/s390x/lower.isle line 1147. + // Rule at src/isa/s390x/lower.isle line 1152. let expr0_0 = constructor_stack_addr_impl(ctx, pattern2_0, pattern4_1, pattern4_2)?; let expr1_0 = C::value_reg(ctx, expr0_0); @@ -7682,14 +7980,14 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Bconst = &pattern4_0 { if pattern4_1 == true { - // Rule at src/isa/s390x/lower.isle line 18. + // Rule at src/isa/s390x/lower.isle line 23. let expr0_0: u64 = 1; let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); return Some(expr2_0); } if pattern4_1 == false { - // Rule at src/isa/s390x/lower.isle line 16. + // Rule at src/isa/s390x/lower.isle line 21. let expr0_0: u64 = 0; let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); @@ -7704,7 +8002,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, &pattern4_1); - // Rule at src/isa/s390x/lower.isle line 915. + // Rule at src/isa/s390x/lower.isle line 920. let expr0_0 = C::put_in_reg(ctx, pattern6_0); let expr1_0 = C::put_in_reg(ctx, pattern6_1); let expr2_0 = constructor_fadd_reg(ctx, pattern2_0, expr0_0, expr1_0)?; @@ -7713,7 +8011,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, &pattern4_1); - // Rule at src/isa/s390x/lower.isle line 922. + // Rule at src/isa/s390x/lower.isle line 927. let expr0_0 = C::put_in_reg(ctx, pattern6_0); let expr1_0 = C::put_in_reg(ctx, pattern6_1); let expr2_0 = constructor_fsub_reg(ctx, pattern2_0, expr0_0, expr1_0)?; @@ -7722,7 +8020,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, &pattern4_1); - // Rule at src/isa/s390x/lower.isle line 929. + // Rule at src/isa/s390x/lower.isle line 934. let expr0_0 = C::put_in_reg(ctx, pattern6_0); let expr1_0 = C::put_in_reg(ctx, pattern6_1); let expr2_0 = constructor_fmul_reg(ctx, pattern2_0, expr0_0, expr1_0)?; @@ -7731,7 +8029,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, &pattern4_1); - // Rule at src/isa/s390x/lower.isle line 936. + // Rule at src/isa/s390x/lower.isle line 941. let expr0_0 = C::put_in_reg(ctx, pattern6_0); let expr1_0 = C::put_in_reg(ctx, pattern6_1); let expr2_0 = constructor_fdiv_reg(ctx, pattern2_0, expr0_0, expr1_0)?; @@ -7740,7 +8038,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, &pattern4_1); - // Rule at src/isa/s390x/lower.isle line 957. + // Rule at src/isa/s390x/lower.isle line 962. let expr0_0 = C::put_in_reg(ctx, pattern6_0); let expr1_0 = C::put_in_reg(ctx, pattern6_1); let expr2_0 = constructor_fpu_copysign(ctx, pattern2_0, expr0_0, expr1_0)?; @@ -7749,7 +8047,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, &pattern4_1); - // Rule at src/isa/s390x/lower.isle line 943. + // Rule at src/isa/s390x/lower.isle line 948. let expr0_0 = C::put_in_reg(ctx, pattern6_0); let expr1_0 = C::put_in_reg(ctx, pattern6_1); let expr2_0 = constructor_fmin_reg(ctx, pattern2_0, expr0_0, expr1_0)?; @@ -7758,7 +8056,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, &pattern4_1); - // Rule at src/isa/s390x/lower.isle line 950. + // Rule at src/isa/s390x/lower.isle line 955. let expr0_0 = C::put_in_reg(ctx, pattern6_0); let expr1_0 = C::put_in_reg(ctx, pattern6_1); let expr2_0 = constructor_fmax_reg(ctx, pattern2_0, expr0_0, expr1_0)?; @@ -7775,7 +8073,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Fcmp = &pattern4_0 { let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, &pattern4_1); - // Rule at src/isa/s390x/lower.isle line 1722. + // Rule at src/isa/s390x/lower.isle line 1727. let expr0_0 = constructor_fcmp_val(ctx, &pattern4_2, pattern6_0, pattern6_1)?; let expr1_0 = constructor_lower_bool(ctx, pattern2_0, &expr0_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); @@ -7789,7 +8087,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Icmp = &pattern4_0 { let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, &pattern4_1); - // Rule at src/isa/s390x/lower.isle line 1633. + // Rule at src/isa/s390x/lower.isle line 1638. let expr0_0: bool = true; let expr1_0 = constructor_icmp_val(ctx, expr0_0, &pattern4_2, pattern6_0, pattern6_1)?; @@ -7806,7 +8104,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern6_0, pattern6_1, pattern6_2) = C::unpack_value_array_3(ctx, &pattern4_1); - // Rule at src/isa/s390x/lower.isle line 1764. + // Rule at src/isa/s390x/lower.isle line 1769. let expr0_0 = constructor_value_nonzero(ctx, pattern6_0)?; let expr1_0 = C::put_in_reg(ctx, pattern6_1); let expr2_0 = C::put_in_reg(ctx, pattern6_2); @@ -7819,7 +8117,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern6_0, pattern6_1, pattern6_2) = C::unpack_value_array_3(ctx, &pattern4_1); - // Rule at src/isa/s390x/lower.isle line 964. + // Rule at src/isa/s390x/lower.isle line 969. let expr0_0 = C::put_in_reg(ctx, pattern6_0); let expr1_0 = C::put_in_reg(ctx, pattern6_1); let expr2_0 = C::put_in_reg(ctx, pattern6_2); @@ -7849,7 +8147,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { match &pattern4_0 { &Opcode::Sqrt => { - // Rule at src/isa/s390x/lower.isle line 971. + // Rule at src/isa/s390x/lower.isle line 976. let expr0_0 = C::put_in_reg(ctx, pattern4_1); let expr1_0 = constructor_sqrt_reg(ctx, pattern2_0, expr0_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); return Some(expr2_0); } &Opcode::Fneg => { - // Rule at src/isa/s390x/lower.isle line 978. + // Rule at src/isa/s390x/lower.isle line 983. let expr0_0 = C::put_in_reg(ctx, pattern4_1); let expr1_0 = constructor_fneg_reg(ctx, pattern2_0, expr0_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); return Some(expr2_0); } &Opcode::Fabs => { - // Rule at src/isa/s390x/lower.isle line 985. + // Rule at src/isa/s390x/lower.isle line 990. let expr0_0 = C::put_in_reg(ctx, pattern4_1); let expr1_0 = constructor_fabs_reg(ctx, pattern2_0, expr0_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); return Some(expr2_0); } &Opcode::Ceil => { - // Rule at src/isa/s390x/lower.isle line 992. + // Rule at src/isa/s390x/lower.isle line 997. let expr0_0 = C::put_in_reg(ctx, pattern4_1); let expr1_0 = constructor_ceil_reg(ctx, pattern2_0, expr0_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); return Some(expr2_0); } &Opcode::Floor => { - // Rule at src/isa/s390x/lower.isle line 999. + // Rule at src/isa/s390x/lower.isle line 1004. let expr0_0 = C::put_in_reg(ctx, pattern4_1); let expr1_0 = constructor_floor_reg(ctx, pattern2_0, expr0_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); return Some(expr2_0); } &Opcode::Trunc => { - // Rule at src/isa/s390x/lower.isle line 1006. + // Rule at src/isa/s390x/lower.isle line 1011. let expr0_0 = C::put_in_reg(ctx, pattern4_1); let expr1_0 = constructor_trunc_reg(ctx, pattern2_0, expr0_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); return Some(expr2_0); } &Opcode::Nearest => { - // Rule at src/isa/s390x/lower.isle line 1013. + // Rule at src/isa/s390x/lower.isle line 1018. let expr0_0 = C::put_in_reg(ctx, pattern4_1); let expr1_0 = constructor_nearest_reg(ctx, pattern2_0, expr0_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); return Some(expr2_0); } &Opcode::Bextend => { - // Rule at src/isa/s390x/lower.isle line 755. + // Rule at src/isa/s390x/lower.isle line 760. let expr0_0 = constructor_cast_bool(ctx, pattern2_0, pattern4_1)?; let expr1_0 = C::value_reg(ctx, expr0_0); return Some(expr1_0); } &Opcode::Bmask => { - // Rule at src/isa/s390x/lower.isle line 757. + // Rule at src/isa/s390x/lower.isle line 762. let expr0_0 = constructor_cast_bool(ctx, pattern2_0, pattern4_1)?; let expr1_0 = C::value_reg(ctx, expr0_0); return Some(expr1_0); } &Opcode::Fpromote => { let pattern6_0 = C::value_type(ctx, pattern4_1); - // Rule at src/isa/s390x/lower.isle line 1020. + // Rule at src/isa/s390x/lower.isle line 1025. let expr0_0 = C::put_in_reg(ctx, pattern4_1); let expr1_0 = constructor_fpromote_reg(ctx, pattern2_0, pattern6_0, expr0_0)?; @@ -7947,7 +8245,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let pattern6_0 = C::value_type(ctx, pattern4_1); - // Rule at src/isa/s390x/lower.isle line 1027. + // Rule at src/isa/s390x/lower.isle line 1032. let expr0_0 = C::put_in_reg(ctx, pattern4_1); let expr1_0 = constructor_fdemote_reg(ctx, pattern2_0, pattern6_0, expr0_0)?; @@ -7956,7 +8254,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let pattern6_0 = C::value_type(ctx, pattern4_1); - // Rule at src/isa/s390x/lower.isle line 1034. + // Rule at src/isa/s390x/lower.isle line 1039. let expr0_0 = constructor_ty_ext32(ctx, pattern6_0)?; let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern4_1)?; let expr2_0 = @@ -7966,7 +8264,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let pattern6_0 = C::value_type(ctx, pattern4_1); - // Rule at src/isa/s390x/lower.isle line 1042. + // Rule at src/isa/s390x/lower.isle line 1047. let expr0_0 = constructor_ty_ext32(ctx, pattern6_0)?; let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern4_1)?; let expr2_0 = @@ -7991,7 +8289,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, &pattern6_1); - // Rule at src/isa/s390x/lower.isle line 697. + // Rule at src/isa/s390x/lower.isle line 702. let expr0_0 = C::put_in_reg(ctx, pattern8_0); let expr1_0 = C::put_in_reg(ctx, pattern8_1); let expr2_0 = @@ -8002,7 +8300,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, &pattern6_1); - // Rule at src/isa/s390x/lower.isle line 708. + // Rule at src/isa/s390x/lower.isle line 713. let expr0_0 = C::put_in_reg(ctx, pattern8_0); let expr1_0 = C::put_in_reg(ctx, pattern8_1); let expr2_0 = @@ -8013,7 +8311,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, &pattern6_1); - // Rule at src/isa/s390x/lower.isle line 719. + // Rule at src/isa/s390x/lower.isle line 724. let expr0_0 = C::put_in_reg(ctx, pattern8_0); let expr1_0 = C::put_in_reg(ctx, pattern8_1); let expr2_0 = @@ -8031,7 +8329,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { match &pattern6_0 { &Opcode::Bnot => { - // Rule at src/isa/s390x/lower.isle line 620. + // Rule at src/isa/s390x/lower.isle line 625. let expr0_0 = C::put_in_reg(ctx, pattern6_1); let expr1_0 = constructor_or_not_reg(ctx, pattern4_0, expr0_0, expr0_0)?; @@ -8057,7 +8355,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { - // Rule at src/isa/s390x/lower.isle line 884. + // Rule at src/isa/s390x/lower.isle line 889. let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern6_1)?; let expr1_0 = constructor_popcnt_reg(ctx, expr0_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); @@ -8079,7 +8377,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, &pattern6_1); - // Rule at src/isa/s390x/lower.isle line 701. + // Rule at src/isa/s390x/lower.isle line 706. let expr0_0 = C::put_in_reg(ctx, pattern8_0); let expr1_0 = C::put_in_reg(ctx, pattern8_1); let expr2_0 = @@ -8181,7 +8479,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, &pattern6_1); - // Rule at src/isa/s390x/lower.isle line 712. + // Rule at src/isa/s390x/lower.isle line 717. let expr0_0 = C::put_in_reg(ctx, pattern8_0); let expr1_0 = C::put_in_reg(ctx, pattern8_1); let expr2_0 = @@ -8193,7 +8491,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, &pattern6_1); - // Rule at src/isa/s390x/lower.isle line 723. + // Rule at src/isa/s390x/lower.isle line 728. let expr0_0 = C::put_in_reg(ctx, pattern8_0); let expr1_0 = C::put_in_reg(ctx, pattern8_1); let expr2_0 = @@ -8212,7 +8510,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Bnot = &pattern6_0 { - // Rule at src/isa/s390x/lower.isle line 625. + // Rule at src/isa/s390x/lower.isle line 630. let expr0_0 = C::put_in_reg(ctx, pattern6_1); let expr1_0 = constructor_not_reg(ctx, pattern4_0, expr0_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); @@ -8252,7 +8550,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let Some(()) = C::bigendian(ctx, pattern10_2) { - // Rule at src/isa/s390x/lower.isle line 89. + // Rule at src/isa/s390x/lower.isle line 94. let expr0_0 = C::put_in_reg(ctx, pattern7_1); let expr1_0 = constructor_sink_sload16(ctx, pattern8_0)?; @@ -8445,7 +8743,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let Some(()) = C::bigendian(ctx, pattern10_2) { - // Rule at src/isa/s390x/lower.isle line 93. + // Rule at src/isa/s390x/lower.isle line 98. let expr0_0 = C::put_in_reg(ctx, pattern7_1); let expr1_0 = constructor_sink_sload32(ctx, pattern8_0)?; @@ -8473,7 +8771,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let Some(()) = C::bigendian(ctx, pattern10_2) { - // Rule at src/isa/s390x/lower.isle line 87. + // Rule at src/isa/s390x/lower.isle line 92. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = constructor_sink_sload16(ctx, pattern8_0)?; @@ -8576,7 +8874,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let Some(()) = C::bigendian(ctx, pattern10_2) { - // Rule at src/isa/s390x/lower.isle line 91. + // Rule at src/isa/s390x/lower.isle line 96. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = constructor_sink_sload32(ctx, pattern8_0)?; @@ -8604,7 +8902,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let Some(()) = C::bigendian(ctx, pattern10_2) { - // Rule at src/isa/s390x/lower.isle line 122. + // Rule at src/isa/s390x/lower.isle line 127. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = constructor_sink_sload16(ctx, pattern8_0)?; @@ -8717,7 +9015,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let Some(()) = C::bigendian(ctx, pattern10_2) { - // Rule at src/isa/s390x/lower.isle line 124. + // Rule at src/isa/s390x/lower.isle line 129. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = constructor_sink_sload32(ctx, pattern8_0)?; @@ -8745,7 +9043,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let Some(()) = C::bigendian(ctx, pattern10_2) { - // Rule at src/isa/s390x/lower.isle line 229. + // Rule at src/isa/s390x/lower.isle line 234. let expr0_0 = C::put_in_reg(ctx, pattern7_1); let expr1_0 = constructor_sink_sload16(ctx, pattern8_0)?; @@ -8858,7 +9156,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let Some(()) = C::bigendian(ctx, pattern10_2) { - // Rule at src/isa/s390x/lower.isle line 233. + // Rule at src/isa/s390x/lower.isle line 238. let expr0_0 = C::put_in_reg(ctx, pattern7_1); let expr1_0 = constructor_sink_sload32(ctx, pattern8_0)?; @@ -8886,7 +9184,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let Some(()) = C::bigendian(ctx, pattern10_2) { - // Rule at src/isa/s390x/lower.isle line 227. + // Rule at src/isa/s390x/lower.isle line 232. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = constructor_sink_sload16(ctx, pattern8_0)?; @@ -8989,7 +9287,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let Some(()) = C::bigendian(ctx, pattern10_2) { - // Rule at src/isa/s390x/lower.isle line 231. + // Rule at src/isa/s390x/lower.isle line 236. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = constructor_sink_sload32(ctx, pattern8_0)?; @@ -9017,7 +9315,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/s390x/lower.isle line 298. + // Rule at src/isa/s390x/lower.isle line 303. let expr0_0 = constructor_zero_divisor_check_needed(ctx, pattern7_1)?; let expr1_0 = constructor_ty_ext32(ctx, pattern3_0)?; let expr2_0: u64 = 0; @@ -9090,7 +9388,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/s390x/lower.isle line 370. + // Rule at src/isa/s390x/lower.isle line 375. let expr0_0 = constructor_zero_divisor_check_needed(ctx, pattern7_1)?; let expr1_0 = constructor_div_overflow_check_needed(ctx, pattern7_1)?; let expr2_0 = constructor_uninitialized_regpair(ctx)?; @@ -9113,7 +9411,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/s390x/lower.isle line 321. + // Rule at src/isa/s390x/lower.isle line 326. let expr0_0 = constructor_zero_divisor_check_needed(ctx, pattern7_1)?; let expr1_0: u64 = 0; let expr2_0 = constructor_uninitialized_regpair(ctx)?; @@ -9135,7 +9433,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/s390x/lower.isle line 393. + // Rule at src/isa/s390x/lower.isle line 398. let expr0_0 = constructor_zero_divisor_check_needed(ctx, pattern7_1)?; let expr1_0 = constructor_div_overflow_check_needed(ctx, pattern7_1)?; let expr2_0 = constructor_uninitialized_regpair(ctx)?; @@ -9159,7 +9457,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { - // Rule at src/isa/s390x/lower.isle line 816. + // Rule at src/isa/s390x/lower.isle line 821. let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern5_1)?; let expr1_0: i16 = 64; let expr2_0 = constructor_clz_reg(ctx, expr1_0, expr0_0)?; @@ -9764,7 +10062,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { - // Rule at src/isa/s390x/lower.isle line 831. + // Rule at src/isa/s390x/lower.isle line 836. let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern5_1)?; let expr1_0: Type = I64; let expr2_0: u8 = 63; @@ -9779,7 +10077,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { - // Rule at src/isa/s390x/lower.isle line 799. + // Rule at src/isa/s390x/lower.isle line 804. let expr0_0 = C::put_in_reg(ctx, pattern5_1); let expr1_0: u64 = 1; let expr2_0 = constructor_imm(ctx, pattern3_0, expr1_0)?; @@ -9805,7 +10103,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { - // Rule at src/isa/s390x/lower.isle line 1514. + // Rule at src/isa/s390x/lower.isle line 1519. let expr0_0 = C::put_in_reg(ctx, pattern7_1); let expr1_0 = C::zero_offset(ctx); let expr2_0 = constructor_lower_address( @@ -9867,7 +10165,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { - // Rule at src/isa/s390x/lower.isle line 1496. + // Rule at src/isa/s390x/lower.isle line 1501. let expr0_0 = C::put_in_reg(ctx, pattern7_1); let expr1_0 = C::zero_offset(ctx); let expr2_0 = constructor_lower_address( @@ -9880,7 +10178,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { - // Rule at src/isa/s390x/lower.isle line 1502. + // Rule at src/isa/s390x/lower.isle line 1507. let expr0_0 = C::put_in_reg(ctx, pattern7_1); let expr1_0 = C::zero_offset(ctx); let expr2_0 = constructor_lower_address( @@ -9893,7 +10191,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { - // Rule at src/isa/s390x/lower.isle line 1520. + // Rule at src/isa/s390x/lower.isle line 1525. let expr0_0 = C::put_in_reg(ctx, pattern7_1); let expr1_0 = constructor_neg_reg(ctx, pattern3_0, expr0_0)?; let expr2_0 = C::zero_offset(ctx); @@ -9907,7 +10205,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { - // Rule at src/isa/s390x/lower.isle line 1508. + // Rule at src/isa/s390x/lower.isle line 1513. let expr0_0 = C::put_in_reg(ctx, pattern7_1); let expr1_0 = C::zero_offset(ctx); let expr2_0 = constructor_lower_address( @@ -9931,7 +10229,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let pattern7_0 = C::value_type(ctx, pattern5_1); - // Rule at src/isa/s390x/lower.isle line 1052. + // Rule at src/isa/s390x/lower.isle line 1057. let expr0_0 = C::put_in_reg(ctx, pattern5_1); let expr1_0 = constructor_fcmp_reg(ctx, pattern7_0, expr0_0, expr0_0)?; let expr2_0 = FloatCC::Unordered; @@ -9950,7 +10248,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let pattern7_0 = C::value_type(ctx, pattern5_1); - // Rule at src/isa/s390x/lower.isle line 1093. + // Rule at src/isa/s390x/lower.isle line 1098. let expr0_0 = C::put_in_reg(ctx, pattern5_1); let expr1_0 = constructor_fcvt_to_uint_reg(ctx, pattern3_0, pattern7_0, expr0_0)?; @@ -9966,7 +10264,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let pattern7_0 = C::value_type(ctx, pattern5_1); - // Rule at src/isa/s390x/lower.isle line 1073. + // Rule at src/isa/s390x/lower.isle line 1078. let expr0_0 = C::put_in_reg(ctx, pattern5_1); let expr1_0 = constructor_fcmp_reg(ctx, pattern7_0, expr0_0, expr0_0)?; let expr2_0 = FloatCC::Unordered; @@ -9985,7 +10283,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let pattern7_0 = C::value_type(ctx, pattern5_1); - // Rule at src/isa/s390x/lower.isle line 1110. + // Rule at src/isa/s390x/lower.isle line 1115. let expr0_0 = C::put_in_reg(ctx, pattern5_1); let expr1_0 = constructor_fcvt_to_sint_reg(ctx, pattern3_0, pattern7_0, expr0_0)?; @@ -10015,7 +10313,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/s390x/lower.isle line 240. + // Rule at src/isa/s390x/lower.isle line 245. let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?; let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern7_1)?; let expr2_0: Type = I32; @@ -10028,7 +10326,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/s390x/lower.isle line 262. + // Rule at src/isa/s390x/lower.isle line 267. let expr0_0 = constructor_put_in_reg_sext32(ctx, pattern7_0)?; let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern7_1)?; let expr2_0: Type = I32; @@ -10043,7 +10341,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { match &pattern5_0 { &Opcode::Ctz => { - // Rule at src/isa/s390x/lower.isle line 854. + // Rule at src/isa/s390x/lower.isle line 859. let expr0_0: Type = I64; let expr1_0 = C::put_in_reg(ctx, pattern5_1); let expr2_0 = constructor_ctz_guardbit(ctx, pattern3_0)?; @@ -10133,13 +10431,13 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { - // Rule at src/isa/s390x/lower.isle line 598. + // Rule at src/isa/s390x/lower.isle line 603. let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?; let expr1_0 = C::value_reg(ctx, expr0_0); return Some(expr1_0); } &Opcode::Sextend => { - // Rule at src/isa/s390x/lower.isle line 609. + // Rule at src/isa/s390x/lower.isle line 614. let expr0_0 = constructor_put_in_reg_sext32(ctx, pattern5_1)?; let expr1_0 = C::value_reg(ctx, expr0_0); return Some(expr1_0); @@ -10155,7 +10453,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { match &pattern5_0 { &Opcode::Uload8 => { - // Rule at src/isa/s390x/lower.isle line 1250. + // Rule at src/isa/s390x/lower.isle line 1255. let expr0_0: Type = I8; let expr1_0 = constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?; @@ -10164,7 +10462,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { - // Rule at src/isa/s390x/lower.isle line 1261. + // Rule at src/isa/s390x/lower.isle line 1266. let expr0_0: Type = I8; let expr1_0 = constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?; @@ -10174,7 +10472,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let Some(()) = C::littleendian(ctx, pattern5_2) { - // Rule at src/isa/s390x/lower.isle line 1277. + // Rule at src/isa/s390x/lower.isle line 1282. let expr0_0 = constructor_lower_address( ctx, pattern5_2, pattern5_1, pattern5_3, )?; @@ -10185,7 +10483,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let Some(()) = C::littleendian(ctx, pattern5_2) { - // Rule at src/isa/s390x/lower.isle line 1302. + // Rule at src/isa/s390x/lower.isle line 1307. let expr0_0 = constructor_lower_address( ctx, pattern5_2, pattern5_1, pattern5_3, )?; @@ -10208,7 +10506,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { match &pattern5_0 { &Opcode::Ctz => { - // Rule at src/isa/s390x/lower.isle line 869. + // Rule at src/isa/s390x/lower.isle line 874. let expr0_0 = C::put_in_reg(ctx, pattern5_1); let expr1_0: Type = I64; let expr2_0: Type = I64; @@ -10251,13 +10549,13 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { - // Rule at src/isa/s390x/lower.isle line 602. + // Rule at src/isa/s390x/lower.isle line 607. let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern5_1)?; let expr1_0 = C::value_reg(ctx, expr0_0); return Some(expr1_0); } &Opcode::Sextend => { - // Rule at src/isa/s390x/lower.isle line 613. + // Rule at src/isa/s390x/lower.isle line 618. let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern5_1)?; let expr1_0 = C::value_reg(ctx, expr0_0); return Some(expr1_0); @@ -10273,7 +10571,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { match &pattern5_0 { &Opcode::Uload8 => { - // Rule at src/isa/s390x/lower.isle line 1254. + // Rule at src/isa/s390x/lower.isle line 1259. let expr0_0: Type = I8; let expr1_0 = constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?; @@ -10282,7 +10580,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { - // Rule at src/isa/s390x/lower.isle line 1265. + // Rule at src/isa/s390x/lower.isle line 1270. let expr0_0: Type = I8; let expr1_0 = constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?; @@ -10292,7 +10590,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let Some(()) = C::littleendian(ctx, pattern5_2) { - // Rule at src/isa/s390x/lower.isle line 1288. + // Rule at src/isa/s390x/lower.isle line 1293. let expr0_0 = constructor_lower_address( ctx, pattern5_2, pattern5_1, pattern5_3, )?; @@ -10303,7 +10601,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let Some(()) = C::littleendian(ctx, pattern5_2) { - // Rule at src/isa/s390x/lower.isle line 1313. + // Rule at src/isa/s390x/lower.isle line 1318. let expr0_0 = constructor_lower_address( ctx, pattern5_2, pattern5_1, pattern5_3, )?; @@ -10326,7 +10624,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let Some(()) = C::littleendian(ctx, pattern5_2) { - // Rule at src/isa/s390x/lower.isle line 1327. + // Rule at src/isa/s390x/lower.isle line 1332. let expr0_0 = constructor_lower_address( ctx, pattern5_2, pattern5_1, pattern5_3, )?; @@ -10349,7 +10647,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let Some(()) = C::littleendian(ctx, pattern5_2) { - // Rule at src/isa/s390x/lower.isle line 1341. + // Rule at src/isa/s390x/lower.isle line 1346. let expr0_0 = constructor_lower_address( ctx, pattern5_2, pattern5_1, pattern5_3, )?; @@ -10372,7 +10670,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option( + ctx: &mut C, + arg0: Inst, + arg1: &VecMachLabel, +) -> Option { + let pattern0_0 = arg0; + let pattern1_0 = C::inst_data(ctx, pattern0_0); + match &pattern1_0 { + &InstructionData::BranchTable { + opcode: ref pattern2_0, + arg: pattern2_1, + destination: pattern2_2, + table: pattern2_3, + } => { + if let &Opcode::BrTable = &pattern2_0 { + let pattern4_0 = arg1; + // Rule at src/isa/s390x/lower.isle line 1799. + let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern2_1)?; + let expr1_0: Type = I64; + let expr2_0 = C::vec_length_minus1(ctx, pattern4_0); + let expr3_0 = constructor_icmpu_uimm32(ctx, expr1_0, expr0_0, expr2_0)?; + let expr4_0 = IntCC::UnsignedGreaterThanOrEqual; + let expr5_0 = C::intcc_as_cond(ctx, &expr4_0); + let expr6_0 = constructor_bool(ctx, &expr3_0, &expr5_0)?; + let expr7_0: u8 = 0; + let expr8_0 = C::vec_element(ctx, pattern4_0, expr7_0); + let expr9_0 = constructor_oneway_cond_br_bool(ctx, &expr6_0, expr8_0)?; + let expr10_0 = constructor_value_regs_none(ctx, &expr9_0)?; + let expr11_0: Type = I64; + let expr12_0: u8 = 2; + let expr13_0 = constructor_lshl_imm(ctx, expr11_0, expr0_0, expr12_0)?; + let expr14_0 = constructor_jt_sequence(ctx, expr13_0, pattern4_0)?; + let expr15_0 = constructor_value_regs_none(ctx, &expr14_0)?; + return Some(expr15_0); + } + } + &InstructionData::Branch { + opcode: ref pattern2_0, + args: pattern2_1, + destination: pattern2_2, + } => { + match &pattern2_0 { + &Opcode::Brz => { + let (pattern4_0, pattern4_1) = C::unwrap_head_value_list_1(ctx, pattern2_1); + let pattern5_0 = arg1; + // Rule at src/isa/s390x/lower.isle line 1832. + let expr0_0 = constructor_value_nonzero(ctx, pattern4_0)?; + let expr1_0 = constructor_invert_bool(ctx, &expr0_0)?; + let expr2_0: u8 = 0; + let expr3_0 = C::vec_element(ctx, pattern5_0, expr2_0); + let expr4_0: u8 = 1; + let expr5_0 = C::vec_element(ctx, pattern5_0, expr4_0); + let expr6_0 = constructor_cond_br_bool(ctx, &expr1_0, expr3_0, expr5_0)?; + let expr7_0 = constructor_value_regs_none(ctx, &expr6_0)?; + return Some(expr7_0); + } + &Opcode::Brnz => { + let (pattern4_0, pattern4_1) = C::unwrap_head_value_list_1(ctx, pattern2_1); + let pattern5_0 = arg1; + // Rule at src/isa/s390x/lower.isle line 1843. + let expr0_0 = constructor_value_nonzero(ctx, pattern4_0)?; + let expr1_0: u8 = 0; + let expr2_0 = C::vec_element(ctx, pattern5_0, expr1_0); + let expr3_0: u8 = 1; + let expr4_0 = C::vec_element(ctx, pattern5_0, expr3_0); + let expr5_0 = constructor_cond_br_bool(ctx, &expr0_0, expr2_0, expr4_0)?; + let expr6_0 = constructor_value_regs_none(ctx, &expr5_0)?; + return Some(expr6_0); + } + _ => {} + } + } + &InstructionData::Jump { + opcode: ref pattern2_0, + args: pattern2_1, + destination: pattern2_2, + } => { + if let &Opcode::Jump = &pattern2_0 { + let pattern4_0 = C::value_list_slice(ctx, pattern2_1); + let pattern5_0 = arg1; + // Rule at src/isa/s390x/lower.isle line 1791. + let expr0_0: u8 = 0; + let expr1_0 = C::vec_element(ctx, pattern5_0, expr0_0); + let expr2_0 = constructor_jump_impl(ctx, expr1_0)?; + let expr3_0 = constructor_value_regs_none(ctx, &expr2_0)?; + return Some(expr3_0); + } + } + &InstructionData::BranchInt { + opcode: ref pattern2_0, + args: pattern2_1, + cond: ref pattern2_2, + destination: pattern2_3, + } => { + if let &Opcode::Brif = &pattern2_0 { + let (pattern4_0, pattern4_1) = C::unwrap_head_value_list_1(ctx, pattern2_1); + if let Some(pattern5_0) = C::def_inst(ctx, pattern4_0) { + let pattern6_0 = C::inst_data(ctx, pattern5_0); + if let &InstructionData::Binary { + opcode: ref pattern7_0, + args: ref pattern7_1, + } = &pattern6_0 + { + if let &Opcode::Ifcmp = &pattern7_0 { + let (pattern9_0, pattern9_1) = + C::unpack_value_array_2(ctx, &pattern7_1); + let pattern10_0 = arg1; + // Rule at src/isa/s390x/lower.isle line 1854. + let expr0_0: bool = false; + let expr1_0 = constructor_icmp_val( + ctx, + expr0_0, + &pattern2_2, + pattern9_0, + pattern9_1, + )?; + let expr2_0: u8 = 0; + let expr3_0 = C::vec_element(ctx, pattern10_0, expr2_0); + let expr4_0: u8 = 1; + let expr5_0 = C::vec_element(ctx, pattern10_0, expr4_0); + let expr6_0 = + constructor_cond_br_bool(ctx, &expr1_0, expr3_0, expr5_0)?; + let expr7_0 = constructor_value_regs_none(ctx, &expr6_0)?; + return Some(expr7_0); + } + } + } + } + } + _ => {} + } + return None; +} + // Generated as internal constructor for term value_regs_ifcout. pub fn constructor_value_regs_ifcout(ctx: &mut C, arg0: Reg) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/s390x/lower.isle line 149. + // Rule at src/isa/s390x/lower.isle line 154. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = C::writable_reg_to_reg(ctx, expr1_0); @@ -10409,18 +10842,18 @@ pub fn constructor_zero_divisor_check_needed(ctx: &mut C, arg0: Valu if let Some(pattern1_0) = C::i64_from_value(ctx, pattern0_0) { let pattern2_0 = 0; if let Some(pattern3_0) = C::i64_nonequal(ctx, pattern1_0, pattern2_0) { - // Rule at src/isa/s390x/lower.isle line 339. + // Rule at src/isa/s390x/lower.isle line 344. let expr0_0: bool = false; return Some(expr0_0); } } let pattern1_0 = C::value_type(ctx, pattern0_0); if let Some(()) = C::allow_div_traps(ctx, pattern1_0) { - // Rule at src/isa/s390x/lower.isle line 340. + // Rule at src/isa/s390x/lower.isle line 345. let expr0_0: bool = false; return Some(expr0_0); } - // Rule at src/isa/s390x/lower.isle line 341. + // Rule at src/isa/s390x/lower.isle line 346. let expr0_0: bool = true; return Some(expr0_0); } @@ -10436,7 +10869,7 @@ pub fn constructor_maybe_trap_if_zero_divisor( if pattern0_0 == true { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/lower.isle line 347. + // Rule at src/isa/s390x/lower.isle line 352. let expr0_0: i16 = 0; let expr1_0 = IntCC::Equal; let expr2_0 = C::intcc_as_cond(ctx, &expr1_0); @@ -10449,7 +10882,7 @@ pub fn constructor_maybe_trap_if_zero_divisor( if pattern0_0 == false { let pattern2_0 = arg1; let pattern3_0 = arg2; - // Rule at src/isa/s390x/lower.isle line 346. + // Rule at src/isa/s390x/lower.isle line 351. let expr0_0 = C::invalid_reg(ctx); return Some(expr0_0); } @@ -10462,12 +10895,12 @@ pub fn constructor_div_overflow_check_needed(ctx: &mut C, arg0: Valu if let Some(pattern1_0) = C::i64_from_value(ctx, pattern0_0) { let pattern2_0 = -1; if let Some(pattern3_0) = C::i64_nonequal(ctx, pattern1_0, pattern2_0) { - // Rule at src/isa/s390x/lower.isle line 420. + // Rule at src/isa/s390x/lower.isle line 425. let expr0_0: bool = false; return Some(expr0_0); } } - // Rule at src/isa/s390x/lower.isle line 421. + // Rule at src/isa/s390x/lower.isle line 426. let expr0_0: bool = true; return Some(expr0_0); } @@ -10487,7 +10920,7 @@ pub fn constructor_maybe_trap_if_sdiv_overflow( let pattern3_0 = arg2; let pattern4_0 = arg3; let pattern5_0 = arg4; - // Rule at src/isa/s390x/lower.isle line 434. + // Rule at src/isa/s390x/lower.isle line 439. let expr0_0 = constructor_int_max(ctx, pattern3_0)?; let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?; let expr2_0 = constructor_regpair_lo(ctx, pattern4_0)?; @@ -10507,7 +10940,7 @@ pub fn constructor_maybe_trap_if_sdiv_overflow( let pattern3_0 = arg2; let pattern4_0 = arg3; let pattern5_0 = arg4; - // Rule at src/isa/s390x/lower.isle line 433. + // Rule at src/isa/s390x/lower.isle line 438. let expr0_0 = C::invalid_reg(ctx); return Some(expr0_0); } @@ -10518,22 +10951,22 @@ pub fn constructor_maybe_trap_if_sdiv_overflow( pub fn constructor_int_max(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I8 { - // Rule at src/isa/s390x/lower.isle line 442. + // Rule at src/isa/s390x/lower.isle line 447. let expr0_0: u64 = 127; return Some(expr0_0); } if pattern0_0 == I16 { - // Rule at src/isa/s390x/lower.isle line 443. + // Rule at src/isa/s390x/lower.isle line 448. let expr0_0: u64 = 32767; return Some(expr0_0); } if pattern0_0 == I32 { - // Rule at src/isa/s390x/lower.isle line 444. + // Rule at src/isa/s390x/lower.isle line 449. let expr0_0: u64 = 2147483647; return Some(expr0_0); } if pattern0_0 == I64 { - // Rule at src/isa/s390x/lower.isle line 445. + // Rule at src/isa/s390x/lower.isle line 450. let expr0_0: u64 = 9223372036854775807; return Some(expr0_0); } @@ -10554,13 +10987,13 @@ pub fn constructor_maybe_avoid_srem_overflow( if pattern2_0 == I32 { let pattern4_0 = arg2; let pattern5_0 = arg3; - // Rule at src/isa/s390x/lower.isle line 463. + // Rule at src/isa/s390x/lower.isle line 468. return Some(pattern4_0.clone()); } if pattern2_0 == I64 { let pattern4_0 = arg2; let pattern5_0 = arg3; - // Rule at src/isa/s390x/lower.isle line 464. + // Rule at src/isa/s390x/lower.isle line 469. let expr0_0: Type = I64; let expr1_0: Type = I64; let expr2_0: i16 = -1; @@ -10578,7 +11011,7 @@ pub fn constructor_maybe_avoid_srem_overflow( let pattern2_0 = arg1; let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/s390x/lower.isle line 462. + // Rule at src/isa/s390x/lower.isle line 467. return Some(pattern3_0.clone()); } return None; @@ -10591,12 +11024,12 @@ pub fn constructor_cast_bool(ctx: &mut C, arg0: Type, arg1: Value) - let pattern2_0 = arg1; let pattern3_0 = C::value_type(ctx, pattern2_0); if pattern3_0 == B1 { - // Rule at src/isa/s390x/lower.isle line 761. + // Rule at src/isa/s390x/lower.isle line 766. let expr0_0 = C::put_in_reg(ctx, pattern2_0); return Some(expr0_0); } if pattern3_0 == B8 { - // Rule at src/isa/s390x/lower.isle line 762. + // Rule at src/isa/s390x/lower.isle line 767. let expr0_0 = C::put_in_reg(ctx, pattern2_0); return Some(expr0_0); } @@ -10605,7 +11038,7 @@ pub fn constructor_cast_bool(ctx: &mut C, arg0: Type, arg1: Value) - let pattern2_0 = arg1; let pattern3_0 = C::value_type(ctx, pattern2_0); if pattern3_0 == B8 { - // Rule at src/isa/s390x/lower.isle line 763. + // Rule at src/isa/s390x/lower.isle line 768. let expr0_0 = C::put_in_reg(ctx, pattern2_0); return Some(expr0_0); } @@ -10614,7 +11047,7 @@ pub fn constructor_cast_bool(ctx: &mut C, arg0: Type, arg1: Value) - let pattern2_0 = arg1; let pattern3_0 = C::value_type(ctx, pattern2_0); if pattern3_0 == B8 { - // Rule at src/isa/s390x/lower.isle line 764. + // Rule at src/isa/s390x/lower.isle line 769. let expr0_0 = C::put_in_reg(ctx, pattern2_0); return Some(expr0_0); } @@ -10623,7 +11056,7 @@ pub fn constructor_cast_bool(ctx: &mut C, arg0: Type, arg1: Value) - let pattern2_0 = arg1; let pattern3_0 = C::value_type(ctx, pattern2_0); if pattern3_0 == B16 { - // Rule at src/isa/s390x/lower.isle line 765. + // Rule at src/isa/s390x/lower.isle line 770. let expr0_0 = C::put_in_reg(ctx, pattern2_0); return Some(expr0_0); } @@ -10632,7 +11065,7 @@ pub fn constructor_cast_bool(ctx: &mut C, arg0: Type, arg1: Value) - let pattern2_0 = arg1; let pattern3_0 = C::value_type(ctx, pattern2_0); if pattern3_0 == B32 { - // Rule at src/isa/s390x/lower.isle line 766. + // Rule at src/isa/s390x/lower.isle line 771. let expr0_0 = C::put_in_reg(ctx, pattern2_0); return Some(expr0_0); } @@ -10641,7 +11074,7 @@ pub fn constructor_cast_bool(ctx: &mut C, arg0: Type, arg1: Value) - let pattern2_0 = arg1; let pattern3_0 = C::value_type(ctx, pattern2_0); if pattern3_0 == B64 { - // Rule at src/isa/s390x/lower.isle line 767. + // Rule at src/isa/s390x/lower.isle line 772. let expr0_0 = C::put_in_reg(ctx, pattern2_0); return Some(expr0_0); } @@ -10650,7 +11083,7 @@ pub fn constructor_cast_bool(ctx: &mut C, arg0: Type, arg1: Value) - let pattern2_0 = arg1; let pattern3_0 = C::value_type(ctx, pattern2_0); if pattern3_0 == B1 { - // Rule at src/isa/s390x/lower.isle line 770. + // Rule at src/isa/s390x/lower.isle line 775. let expr0_0: Type = I32; let expr1_0: Type = I32; let expr2_0 = C::put_in_reg(ctx, pattern2_0); @@ -10661,14 +11094,14 @@ pub fn constructor_cast_bool(ctx: &mut C, arg0: Type, arg1: Value) - return Some(expr6_0); } if pattern3_0 == B8 { - // Rule at src/isa/s390x/lower.isle line 776. + // Rule at src/isa/s390x/lower.isle line 781. let expr0_0: Type = I8; let expr1_0 = C::put_in_reg(ctx, pattern2_0); let expr2_0 = constructor_sext32_reg(ctx, expr0_0, expr1_0)?; return Some(expr2_0); } if pattern3_0 == B16 { - // Rule at src/isa/s390x/lower.isle line 778. + // Rule at src/isa/s390x/lower.isle line 783. let expr0_0: Type = I16; let expr1_0 = C::put_in_reg(ctx, pattern2_0); let expr2_0 = constructor_sext32_reg(ctx, expr0_0, expr1_0)?; @@ -10679,7 +11112,7 @@ pub fn constructor_cast_bool(ctx: &mut C, arg0: Type, arg1: Value) - let pattern2_0 = arg1; let pattern3_0 = C::value_type(ctx, pattern2_0); if pattern3_0 == B1 { - // Rule at src/isa/s390x/lower.isle line 772. + // Rule at src/isa/s390x/lower.isle line 777. let expr0_0: Type = I64; let expr1_0: Type = I64; let expr2_0 = C::put_in_reg(ctx, pattern2_0); @@ -10690,21 +11123,21 @@ pub fn constructor_cast_bool(ctx: &mut C, arg0: Type, arg1: Value) - return Some(expr6_0); } if pattern3_0 == B8 { - // Rule at src/isa/s390x/lower.isle line 780. + // Rule at src/isa/s390x/lower.isle line 785. let expr0_0: Type = I8; let expr1_0 = C::put_in_reg(ctx, pattern2_0); let expr2_0 = constructor_sext64_reg(ctx, expr0_0, expr1_0)?; return Some(expr2_0); } if pattern3_0 == B16 { - // Rule at src/isa/s390x/lower.isle line 782. + // Rule at src/isa/s390x/lower.isle line 787. let expr0_0: Type = I16; let expr1_0 = C::put_in_reg(ctx, pattern2_0); let expr2_0 = constructor_sext64_reg(ctx, expr0_0, expr1_0)?; return Some(expr2_0); } if pattern3_0 == B32 { - // Rule at src/isa/s390x/lower.isle line 784. + // Rule at src/isa/s390x/lower.isle line 789. let expr0_0: Type = I32; let expr1_0 = C::put_in_reg(ctx, pattern2_0); let expr2_0 = constructor_sext64_reg(ctx, expr0_0, expr1_0)?; @@ -10719,7 +11152,7 @@ pub fn constructor_clz_offset(ctx: &mut C, arg0: Type, arg1: Reg) -> let pattern0_0 = arg0; if pattern0_0 == I8 { let pattern2_0 = arg1; - // Rule at src/isa/s390x/lower.isle line 809. + // Rule at src/isa/s390x/lower.isle line 814. let expr0_0: Type = I8; let expr1_0: i16 = -56; let expr2_0 = constructor_add_simm16(ctx, expr0_0, pattern2_0, expr1_0)?; @@ -10727,7 +11160,7 @@ pub fn constructor_clz_offset(ctx: &mut C, arg0: Type, arg1: Reg) -> } if pattern0_0 == I16 { let pattern2_0 = arg1; - // Rule at src/isa/s390x/lower.isle line 810. + // Rule at src/isa/s390x/lower.isle line 815. let expr0_0: Type = I16; let expr1_0: i16 = -48; let expr2_0 = constructor_add_simm16(ctx, expr0_0, pattern2_0, expr1_0)?; @@ -10735,7 +11168,7 @@ pub fn constructor_clz_offset(ctx: &mut C, arg0: Type, arg1: Reg) -> } if pattern0_0 == I32 { let pattern2_0 = arg1; - // Rule at src/isa/s390x/lower.isle line 811. + // Rule at src/isa/s390x/lower.isle line 816. let expr0_0: Type = I32; let expr1_0: i16 = -32; let expr2_0 = constructor_add_simm16(ctx, expr0_0, pattern2_0, expr1_0)?; @@ -10743,7 +11176,7 @@ pub fn constructor_clz_offset(ctx: &mut C, arg0: Type, arg1: Reg) -> } if pattern0_0 == I64 { let pattern2_0 = arg1; - // Rule at src/isa/s390x/lower.isle line 812. + // Rule at src/isa/s390x/lower.isle line 817. let expr0_0: Type = I64; let expr1_0 = constructor_copy_reg(ctx, expr0_0, pattern2_0)?; return Some(expr1_0); @@ -10755,21 +11188,21 @@ pub fn constructor_clz_offset(ctx: &mut C, arg0: Type, arg1: Reg) -> pub fn constructor_ctz_guardbit(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I8 { - // Rule at src/isa/s390x/lower.isle line 861. + // Rule at src/isa/s390x/lower.isle line 866. let expr0_0: u16 = 256; let expr1_0: u8 = 0; let expr2_0 = C::uimm16shifted(ctx, expr0_0, expr1_0); return Some(expr2_0); } if pattern0_0 == I16 { - // Rule at src/isa/s390x/lower.isle line 862. + // Rule at src/isa/s390x/lower.isle line 867. let expr0_0: u16 = 1; let expr1_0: u8 = 16; let expr2_0 = C::uimm16shifted(ctx, expr0_0, expr1_0); return Some(expr2_0); } if pattern0_0 == I32 { - // Rule at src/isa/s390x/lower.isle line 863. + // Rule at src/isa/s390x/lower.isle line 868. let expr0_0: u16 = 1; let expr1_0: u8 = 32; let expr2_0 = C::uimm16shifted(ctx, expr0_0, expr1_0); @@ -10791,14 +11224,14 @@ pub fn constructor_istore8_impl( if let Some(pattern2_0) = C::u8_from_value(ctx, pattern1_0) { let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/s390x/lower.isle line 1423. + // Rule at src/isa/s390x/lower.isle line 1428. let expr0_0 = constructor_lower_address(ctx, pattern0_0, pattern3_0, pattern4_0)?; let expr1_0 = constructor_store8_imm(ctx, pattern2_0, &expr0_0)?; return Some(expr1_0); } let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/s390x/lower.isle line 1419. + // Rule at src/isa/s390x/lower.isle line 1424. let expr0_0 = C::put_in_reg(ctx, pattern1_0); let expr1_0 = constructor_lower_address(ctx, pattern0_0, pattern2_0, pattern3_0)?; let expr2_0 = constructor_store8(ctx, expr0_0, &expr1_0)?; @@ -10819,14 +11252,14 @@ pub fn constructor_istore16_impl( if let Some(pattern3_0) = C::i16_from_swapped_value(ctx, pattern2_0) { let pattern4_0 = arg2; let pattern5_0 = arg3; - // Rule at src/isa/s390x/lower.isle line 1449. + // Rule at src/isa/s390x/lower.isle line 1454. let expr0_0 = constructor_lower_address(ctx, pattern0_0, pattern4_0, pattern5_0)?; let expr1_0 = constructor_store16_imm(ctx, pattern3_0, &expr0_0)?; return Some(expr1_0); } let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/s390x/lower.isle line 1441. + // Rule at src/isa/s390x/lower.isle line 1446. let expr0_0 = C::put_in_reg(ctx, pattern2_0); let expr1_0 = constructor_lower_address(ctx, pattern0_0, pattern3_0, pattern4_0)?; let expr2_0 = constructor_storerev16(ctx, expr0_0, &expr1_0)?; @@ -10837,14 +11270,14 @@ pub fn constructor_istore16_impl( if let Some(pattern3_0) = C::i16_from_value(ctx, pattern2_0) { let pattern4_0 = arg2; let pattern5_0 = arg3; - // Rule at src/isa/s390x/lower.isle line 1445. + // Rule at src/isa/s390x/lower.isle line 1450. let expr0_0 = constructor_lower_address(ctx, pattern0_0, pattern4_0, pattern5_0)?; let expr1_0 = constructor_store16_imm(ctx, pattern3_0, &expr0_0)?; return Some(expr1_0); } let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/s390x/lower.isle line 1437. + // Rule at src/isa/s390x/lower.isle line 1442. let expr0_0 = C::put_in_reg(ctx, pattern2_0); let expr1_0 = constructor_lower_address(ctx, pattern0_0, pattern3_0, pattern4_0)?; let expr2_0 = constructor_store16(ctx, expr0_0, &expr1_0)?; @@ -10866,7 +11299,7 @@ pub fn constructor_istore32_impl( let pattern2_0 = arg1; let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/s390x/lower.isle line 1471. + // Rule at src/isa/s390x/lower.isle line 1476. let expr0_0 = C::put_in_reg(ctx, pattern2_0); let expr1_0 = constructor_lower_address(ctx, pattern0_0, pattern3_0, pattern4_0)?; let expr2_0 = constructor_storerev32(ctx, expr0_0, &expr1_0)?; @@ -10877,14 +11310,14 @@ pub fn constructor_istore32_impl( if let Some(pattern3_0) = C::i16_from_value(ctx, pattern2_0) { let pattern4_0 = arg2; let pattern5_0 = arg3; - // Rule at src/isa/s390x/lower.isle line 1467. + // Rule at src/isa/s390x/lower.isle line 1472. let expr0_0 = constructor_lower_address(ctx, pattern0_0, pattern4_0, pattern5_0)?; let expr1_0 = constructor_store32_simm16(ctx, pattern3_0, &expr0_0)?; return Some(expr1_0); } let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/s390x/lower.isle line 1463. + // Rule at src/isa/s390x/lower.isle line 1468. let expr0_0 = C::put_in_reg(ctx, pattern2_0); let expr1_0 = constructor_lower_address(ctx, pattern0_0, pattern3_0, pattern4_0)?; let expr2_0 = constructor_store32(ctx, expr0_0, &expr1_0)?; @@ -10906,7 +11339,7 @@ pub fn constructor_istore64_impl( let pattern2_0 = arg1; let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/s390x/lower.isle line 1489. + // Rule at src/isa/s390x/lower.isle line 1494. let expr0_0 = C::put_in_reg(ctx, pattern2_0); let expr1_0 = constructor_lower_address(ctx, pattern0_0, pattern3_0, pattern4_0)?; let expr2_0 = constructor_storerev64(ctx, expr0_0, &expr1_0)?; @@ -10917,14 +11350,14 @@ pub fn constructor_istore64_impl( if let Some(pattern3_0) = C::i16_from_value(ctx, pattern2_0) { let pattern4_0 = arg2; let pattern5_0 = arg3; - // Rule at src/isa/s390x/lower.isle line 1485. + // Rule at src/isa/s390x/lower.isle line 1490. let expr0_0 = constructor_lower_address(ctx, pattern0_0, pattern4_0, pattern5_0)?; let expr1_0 = constructor_store64_simm16(ctx, pattern3_0, &expr0_0)?; return Some(expr1_0); } let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/s390x/lower.isle line 1481. + // Rule at src/isa/s390x/lower.isle line 1486. let expr0_0 = C::put_in_reg(ctx, pattern2_0); let expr1_0 = constructor_lower_address(ctx, pattern0_0, pattern3_0, pattern4_0)?; let expr2_0 = constructor_store64(ctx, expr0_0, &expr1_0)?; @@ -10939,7 +11372,7 @@ pub fn constructor_atomic_store_impl( arg0: &SideEffectNoResult, ) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/s390x/lower.isle line 1576. + // Rule at src/isa/s390x/lower.isle line 1581. let expr0_0 = constructor_value_regs_none(ctx, pattern0_0)?; let expr1_0 = constructor_fence_impl(ctx)?; let expr2_0 = constructor_value_regs_none(ctx, &expr1_0)?; @@ -10959,7 +11392,7 @@ pub fn constructor_icmp_val( if let Some(()) = C::signed(ctx, pattern1_0) { let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/s390x/lower.isle line 1643. + // Rule at src/isa/s390x/lower.isle line 1648. let expr0_0 = constructor_icmps_val(ctx, pattern0_0, pattern3_0, pattern4_0)?; let expr1_0 = C::intcc_as_cond(ctx, pattern1_0); let expr2_0 = constructor_bool(ctx, &expr0_0, &expr1_0)?; @@ -10968,7 +11401,7 @@ pub fn constructor_icmp_val( if let Some(()) = C::unsigned(ctx, pattern1_0) { let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/s390x/lower.isle line 1646. + // Rule at src/isa/s390x/lower.isle line 1651. let expr0_0 = constructor_icmpu_val(ctx, pattern0_0, pattern3_0, pattern4_0)?; let expr1_0 = C::intcc_as_cond(ctx, pattern1_0); let expr2_0 = constructor_bool(ctx, &expr0_0, &expr1_0)?; @@ -11002,7 +11435,7 @@ pub fn constructor_icmps_val( match &pattern8_0 { &Opcode::Sload16 => { if let Some(()) = C::bigendian(ctx, pattern8_2) { - // Rule at src/isa/s390x/lower.isle line 1676. + // Rule at src/isa/s390x/lower.isle line 1681. let expr0_0 = C::put_in_reg(ctx, pattern2_0); let expr1_0 = constructor_sink_sload16(ctx, pattern6_0)?; let expr2_0 = constructor_icmps_mem_sext16( @@ -11013,7 +11446,7 @@ pub fn constructor_icmps_val( } &Opcode::Sload32 => { if let Some(()) = C::bigendian(ctx, pattern8_2) { - // Rule at src/isa/s390x/lower.isle line 1678. + // Rule at src/isa/s390x/lower.isle line 1683. let expr0_0 = C::put_in_reg(ctx, pattern2_0); let expr1_0 = constructor_sink_sload32(ctx, pattern6_0)?; let expr2_0 = constructor_icmps_mem_sext32( @@ -11039,7 +11472,7 @@ pub fn constructor_icmps_val( { if let &Opcode::Load = &pattern10_0 { if let Some(()) = C::bigendian(ctx, pattern10_2) { - // Rule at src/isa/s390x/lower.isle line 1672. + // Rule at src/isa/s390x/lower.isle line 1677. let expr0_0 = constructor_ty_ext32(ctx, pattern4_0)?; let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern2_0)?; let expr2_0 = constructor_sink_load(ctx, pattern8_0)?; @@ -11063,7 +11496,7 @@ pub fn constructor_icmps_val( { if let &Opcode::Load = &pattern10_0 { if let Some(()) = C::bigendian(ctx, pattern10_2) { - // Rule at src/isa/s390x/lower.isle line 1668. + // Rule at src/isa/s390x/lower.isle line 1673. let expr0_0 = C::put_in_reg(ctx, pattern2_0); let expr1_0 = constructor_sink_load(ctx, pattern8_0)?; let expr2_0 = @@ -11081,14 +11514,14 @@ pub fn constructor_icmps_val( if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) { let pattern4_0 = arg2; if let Some(pattern5_0) = C::i16_from_value(ctx, pattern4_0) { - // Rule at src/isa/s390x/lower.isle line 1662. + // Rule at src/isa/s390x/lower.isle line 1667. let expr0_0 = constructor_ty_ext32(ctx, pattern3_0)?; let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern1_0)?; let expr2_0 = constructor_icmps_simm16(ctx, expr0_0, expr1_0, pattern5_0)?; return Some(expr2_0); } if let Some(pattern5_0) = C::i32_from_value(ctx, pattern4_0) { - // Rule at src/isa/s390x/lower.isle line 1664. + // Rule at src/isa/s390x/lower.isle line 1669. let expr0_0 = constructor_ty_ext32(ctx, pattern3_0)?; let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern1_0)?; let expr2_0 = constructor_icmps_simm32(ctx, expr0_0, expr1_0, pattern5_0)?; @@ -11104,7 +11537,7 @@ pub fn constructor_icmps_val( if let &Opcode::Sextend = &pattern7_0 { let pattern9_0 = C::value_type(ctx, pattern7_1); if pattern9_0 == I32 { - // Rule at src/isa/s390x/lower.isle line 1658. + // Rule at src/isa/s390x/lower.isle line 1663. let expr0_0 = C::put_in_reg(ctx, pattern1_0); let expr1_0 = C::put_in_reg(ctx, pattern7_1); let expr2_0 = @@ -11114,7 +11547,7 @@ pub fn constructor_icmps_val( } } } - // Rule at src/isa/s390x/lower.isle line 1654. + // Rule at src/isa/s390x/lower.isle line 1659. let expr0_0 = constructor_ty_ext32(ctx, pattern3_0)?; let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern1_0)?; let expr2_0 = constructor_put_in_reg_sext32(ctx, pattern4_0)?; @@ -11175,7 +11608,7 @@ pub fn constructor_icmpu_val( if let Some(()) = C::bigendian(ctx, pattern17_2) { - // Rule at src/isa/s390x/lower.isle line 1711. + // Rule at src/isa/s390x/lower.isle line 1716. let expr0_0 = C::put_in_reg(ctx, pattern2_0); let expr1_0 = constructor_sink_uload16( @@ -11198,7 +11631,7 @@ pub fn constructor_icmpu_val( } &Opcode::Uload32 => { if let Some(()) = C::bigendian(ctx, pattern8_2) { - // Rule at src/isa/s390x/lower.isle line 1714. + // Rule at src/isa/s390x/lower.isle line 1719. let expr0_0 = C::put_in_reg(ctx, pattern2_0); let expr1_0 = constructor_sink_uload32(ctx, pattern6_0)?; let expr2_0 = constructor_icmpu_mem_zext32( @@ -11250,7 +11683,7 @@ pub fn constructor_icmpu_val( if let Some(()) = C::bigendian(ctx, pattern19_2) { - // Rule at src/isa/s390x/lower.isle line 1704. + // Rule at src/isa/s390x/lower.isle line 1709. let expr0_0 = constructor_ty_ext32( ctx, pattern4_0, )?; @@ -11290,7 +11723,7 @@ pub fn constructor_icmpu_val( { if let &Opcode::Load = &pattern10_0 { if let Some(()) = C::bigendian(ctx, pattern10_2) { - // Rule at src/isa/s390x/lower.isle line 1698. + // Rule at src/isa/s390x/lower.isle line 1703. let expr0_0 = C::put_in_reg(ctx, pattern2_0); let expr1_0 = constructor_sink_load(ctx, pattern8_0)?; let expr2_0 = @@ -11308,7 +11741,7 @@ pub fn constructor_icmpu_val( if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) { let pattern4_0 = arg2; if let Some(pattern5_0) = C::u32_from_value(ctx, pattern4_0) { - // Rule at src/isa/s390x/lower.isle line 1694. + // Rule at src/isa/s390x/lower.isle line 1699. let expr0_0 = constructor_ty_ext32(ctx, pattern3_0)?; let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern1_0)?; let expr2_0 = constructor_icmpu_uimm32(ctx, expr0_0, expr1_0, pattern5_0)?; @@ -11324,7 +11757,7 @@ pub fn constructor_icmpu_val( if let &Opcode::Uextend = &pattern7_0 { let pattern9_0 = C::value_type(ctx, pattern7_1); if pattern9_0 == I32 { - // Rule at src/isa/s390x/lower.isle line 1690. + // Rule at src/isa/s390x/lower.isle line 1695. let expr0_0 = C::put_in_reg(ctx, pattern1_0); let expr1_0 = C::put_in_reg(ctx, pattern7_1); let expr2_0 = @@ -11334,7 +11767,7 @@ pub fn constructor_icmpu_val( } } } - // Rule at src/isa/s390x/lower.isle line 1686. + // Rule at src/isa/s390x/lower.isle line 1691. let expr0_0 = constructor_ty_ext32(ctx, pattern3_0)?; let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern1_0)?; let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern4_0)?; @@ -11355,7 +11788,7 @@ pub fn constructor_fcmp_val( let pattern1_0 = arg1; let pattern2_0 = C::value_type(ctx, pattern1_0); let pattern3_0 = arg2; - // Rule at src/isa/s390x/lower.isle line 1727. + // Rule at src/isa/s390x/lower.isle line 1732. let expr0_0 = C::put_in_reg(ctx, pattern1_0); let expr1_0 = C::put_in_reg(ctx, pattern3_0); let expr2_0 = constructor_fcmp_reg(ctx, pattern2_0, expr0_0, expr1_0)?; @@ -11377,7 +11810,7 @@ pub fn constructor_value_nonzero(ctx: &mut C, arg0: Value) -> Option } => { if let &Opcode::Fcmp = &pattern3_0 { let (pattern5_0, pattern5_1) = C::unpack_value_array_2(ctx, &pattern3_1); - // Rule at src/isa/s390x/lower.isle line 1755. + // Rule at src/isa/s390x/lower.isle line 1760. let expr0_0 = constructor_fcmp_val(ctx, &pattern3_2, pattern5_0, pattern5_1)?; return Some(expr0_0); } @@ -11389,7 +11822,7 @@ pub fn constructor_value_nonzero(ctx: &mut C, arg0: Value) -> Option } => { if let &Opcode::Icmp = &pattern3_0 { let (pattern5_0, pattern5_1) = C::unpack_value_array_2(ctx, &pattern3_1); - // Rule at src/isa/s390x/lower.isle line 1754. + // Rule at src/isa/s390x/lower.isle line 1759. let expr0_0: bool = false; let expr1_0 = constructor_icmp_val(ctx, expr0_0, &pattern3_2, pattern5_0, pattern5_1)?; @@ -11401,7 +11834,7 @@ pub fn constructor_value_nonzero(ctx: &mut C, arg0: Value) -> Option arg: pattern3_1, } => { if let &Opcode::Bint = &pattern3_0 { - // Rule at src/isa/s390x/lower.isle line 1753. + // Rule at src/isa/s390x/lower.isle line 1758. let expr0_0 = constructor_value_nonzero(ctx, pattern3_1)?; return Some(expr0_0); } @@ -11411,7 +11844,7 @@ pub fn constructor_value_nonzero(ctx: &mut C, arg0: Value) -> Option } let pattern1_0 = C::value_type(ctx, pattern0_0); if let Some(pattern2_0) = C::gpr32_ty(ctx, pattern1_0) { - // Rule at src/isa/s390x/lower.isle line 1756. + // Rule at src/isa/s390x/lower.isle line 1761. let expr0_0: Type = I32; let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern0_0)?; let expr2_0: i16 = 0; @@ -11422,7 +11855,7 @@ pub fn constructor_value_nonzero(ctx: &mut C, arg0: Value) -> Option return Some(expr6_0); } if let Some(pattern2_0) = C::gpr64_ty(ctx, pattern1_0) { - // Rule at src/isa/s390x/lower.isle line 1759. + // Rule at src/isa/s390x/lower.isle line 1764. let expr0_0: Type = I64; let expr1_0 = C::put_in_reg(ctx, pattern0_0); let expr2_0: i16 = 0; diff --git a/cranelift/codegen/src/machinst/isle.rs b/cranelift/codegen/src/machinst/isle.rs index 369f3d1f66..1869ba6762 100644 --- a/cranelift/codegen/src/machinst/isle.rs +++ b/cranelift/codegen/src/machinst/isle.rs @@ -312,18 +312,19 @@ where /// The `isle_lower` argument here is an ISLE-generated function for `lower` and /// then this function otherwise handles register mapping and such around the /// lowering. -pub(crate) fn lower_common( +pub(crate) fn lower_common( lower_ctx: &mut C, flags: &F, isa_flags: &I, outputs: &[InsnOutput], inst: Inst, - isle_lower: fn(&mut IsleContext<'_, C, F, I, N>, Inst) -> Option, + isle_lower: IF, map_regs: fn(&mut C::I, &RegRenamer), ) -> Result<(), ()> where C: LowerCtx, [(C::I, bool); N]: smallvec::Array, + IF: Fn(&mut IsleContext<'_, C, F, I, N>, Inst) -> Option, { // TODO: reuse the ISLE context across lowerings so we can reuse its // internal heap allocations.