From 3608be35a95ea81f3dbd26d13792771092b568bc Mon Sep 17 00:00:00 2001
From: Jakob Stoklund Olesen <jolesen@mozilla.com>
Date: Fri, 30 Jun 2017 11:41:06 -0700
Subject: [PATCH] Add Intel iconst.i32 encoding.

---
 filetests/isa/intel/binary32.cton        |  6 ++++--
 lib/cretonne/meta/isa/intel/encodings.py |  3 +++
 lib/cretonne/meta/isa/intel/recipes.py   |  7 ++++++-
 lib/cretonne/src/isa/intel/binemit.rs    | 13 +++++++++++++
 4 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/filetests/isa/intel/binary32.cton b/filetests/isa/intel/binary32.cton
index 818335d349..6d13844497 100644
--- a/filetests/isa/intel/binary32.cton
+++ b/filetests/isa/intel/binary32.cton
@@ -9,8 +9,10 @@ isa intel
 
 function %I32() {
 ebb0:
-    [-,%rcx]            v1 = iconst.i32 1
-    [-,%rsi]            v2 = iconst.i32 2
+    ; asm: movl $1, %ecx
+    [-,%rcx]            v1 = iconst.i32 1        ; bin: b9 00000001
+    ; asm: movl $2, %esi
+    [-,%rsi]            v2 = iconst.i32 2        ; bin: be 00000002
 
     ; Integer Register-Register Operations.
 
diff --git a/lib/cretonne/meta/isa/intel/encodings.py b/lib/cretonne/meta/isa/intel/encodings.py
index 575c36baca..4010ffb64a 100644
--- a/lib/cretonne/meta/isa/intel/encodings.py
+++ b/lib/cretonne/meta/isa/intel/encodings.py
@@ -22,6 +22,9 @@ for inst,                   rrr in [
     I32.enc(inst, *r.rib(0x83, rrr=rrr))
     I32.enc(inst, *r.rid(0x81, rrr=rrr))
 
+# Immediate constant.
+I32.enc(base.iconst.i32, *r.uid(0xb8))
+
 # 32-bit shifts and rotates.
 # Note that the dynamic shift amount is only masked by 5 or 6 bits; the 8-bit
 # and 16-bit shifts would need explicit masking.
diff --git a/lib/cretonne/meta/isa/intel/recipes.py b/lib/cretonne/meta/isa/intel/recipes.py
index 71b8260f42..70377f8756 100644
--- a/lib/cretonne/meta/isa/intel/recipes.py
+++ b/lib/cretonne/meta/isa/intel/recipes.py
@@ -4,7 +4,7 @@ Intel Encoding recipes.
 from __future__ import absolute_import
 from cdsl.isa import EncRecipe
 from cdsl.predicates import IsSignedInt, IsEqual
-from base.formats import Binary, BinaryImm, Store, Load
+from base.formats import UnaryImm, Binary, BinaryImm, Store, Load
 from .registers import GPR, ABCD
 
 try:
@@ -155,6 +155,11 @@ rid = TailRecipe(
         'rid', BinaryImm, size=5, ins=GPR, outs=0,
         instp=IsSignedInt(BinaryImm.imm, 32))
 
+# XX+rd id unary with 32-bit immediate.
+uid = TailRecipe(
+        'uid', UnaryImm, size=4, ins=(), outs=GPR,
+        instp=IsSignedInt(UnaryImm.imm, 32))
+
 #
 # Store recipes.
 #
diff --git a/lib/cretonne/src/isa/intel/binemit.rs b/lib/cretonne/src/isa/intel/binemit.rs
index 87587463ca..aded1e41e6 100644
--- a/lib/cretonne/src/isa/intel/binemit.rs
+++ b/lib/cretonne/src/isa/intel/binemit.rs
@@ -133,6 +133,19 @@ fn recipe_op1rid<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut
     }
 }
 
+fn recipe_op1uid<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
+    if let InstructionData::UnaryImm { imm, .. } = func.dfg[inst] {
+        let bits = func.encodings[inst].bits();
+        let reg = func.locations[func.dfg.first_result(inst)].unwrap_reg();
+        // The destination register is encoded in the low bits of the opcode. No ModR/M
+        put_op1(bits | (reg & 7), sink);
+        let imm: i64 = imm.into();
+        sink.put4(imm as u32);
+    } else {
+        panic!("Expected UnaryImm format: {:?}", func.dfg[inst]);
+    }
+}
+
 // Store recipes.
 
 fn recipe_op1st<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {