Generate register bank descriptions.

Use the information in the ISA's registers.py files to generate a
RegInfo Rust data structure.

lib/cretonne/src/isa/riscv/mod.rs

@@ -2,11 +2,12 @@
 
 pub mod settings;
 mod enc_tables;
+mod registers;
 
 use super::super::settings as shared_settings;
 use isa::enc_tables::{self as shared_enc_tables, lookup_enclist, general_encoding};
 use isa::Builder as IsaBuilder;
-use isa::{TargetIsa, Encoding, Legalize};
+use isa::{TargetIsa, RegInfo, Encoding, Legalize};
 use ir::{InstructionData, DataFlowGraph};
 
 #[allow(dead_code)]
@@ -48,6 +49,10 @@ impl TargetIsa for Isa {
         &self.shared_flags
     }
 
+    fn register_info(&self) -> &RegInfo {
+        &registers::INFO
+    }
+
     fn encode(&self, _: &DataFlowGraph, inst: &InstructionData) -> Result<Encoding, Legalize> {
         lookup_enclist(inst.first_type(),
                        inst.opcode(),

lib/cretonne/src/isa/riscv/registers.py

@@ -0,0 +1 @@
+

lib/cretonne/src/isa/riscv/registers.rs

@@ -0,0 +1,37 @@
+//! RISC-V register descriptions.
+
+use isa::registers::{RegBank, RegInfo};
+
+include!(concat!(env!("OUT_DIR"), "/registers-riscv.rs"));
+
+#[cfg(test)]
+mod tests {
+    use super::INFO;
+    use isa::RegUnit;
+
+    #[test]
+    fn unit_encodings() {
+        assert_eq!(INFO.parse_regunit("x0"), Some(0));
+        assert_eq!(INFO.parse_regunit("x31"), Some(31));
+        assert_eq!(INFO.parse_regunit("f0"), Some(32));
+        assert_eq!(INFO.parse_regunit("f31"), Some(63));
+
+        assert_eq!(INFO.parse_regunit("x32"), None);
+        assert_eq!(INFO.parse_regunit("f32"), None);
+    }
+
+    #[test]
+    fn unit_names() {
+        fn uname(ru: RegUnit) -> String {
+            INFO.display_regunit(ru).to_string()
+        }
+
+        assert_eq!(uname(0), "%x0");
+        assert_eq!(uname(1), "%x1");
+        assert_eq!(uname(31), "%x31");
+        assert_eq!(uname(32), "%f0");
+        assert_eq!(uname(33), "%f1");
+        assert_eq!(uname(63), "%f31");
+        assert_eq!(uname(64), "%INVALID64");
+    }
+}