Generate register bank descriptions.

Use the information in the ISA's registers.py files to generate a
RegInfo Rust data structure.

lib/cretonne/meta/isa/arm32/__init__.py

@@ -8,6 +8,7 @@ This target ISA generates code for ARMv7 and ARMv8 CPUs in 32-bit mode
 
 from __future__ import absolute_import
 from . import defs
+from . import registers  # noqa
 
 # Re-export the primary target ISA definition.
 ISA = defs.ISA.finish()

lib/cretonne/meta/isa/arm64/__init__.py

@@ -7,6 +7,7 @@ ARMv8 CPUs running the Aarch64 architecture.
 
 from __future__ import absolute_import
 from . import defs
+from . import registers  # noqa
 
 # Re-export the primary target ISA definition.
 ISA = defs.ISA.finish()

lib/cretonne/meta/isa/intel/__init__.py

@@ -17,6 +17,7 @@ is no x87 floating point support.
 
 from __future__ import absolute_import
 from . import defs
+from . import registers  # noqa
 
 # Re-export the primary target ISA definition.
 ISA = defs.ISA.finish()

lib/cretonne/meta/isa/riscv/__init__.py

@@ -26,7 +26,7 @@ RV32G / RV64G
 """
 from __future__ import absolute_import
 from . import defs
-from . import encodings, settings # noqa
+from . import encodings, settings, registers  # noqa
 
 # Re-export the primary target ISA definition.
 ISA = defs.ISA.finish()