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[codegen] reintroduce support for carry and borrow instructions in RI… (#1005)

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Reintroduce support for iadd carry variants and isub borrow variants for
RISC ISAs which had been removed in
https://github.com/CraneStation/cranelift/pull/961 and
https://github.com/CraneStation/cranelift/pull/962 because of the lack
of a proper flags register in RISC architectures.
This commit is contained in:
Ujjwal Sharma
2019-09-13 20:57:50 +05:30
committed by Benjamin Bouvier
parent cadd0ac655
commit 3418fb6e18
17 changed files with 326 additions and 85 deletions
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4
cranelift/filetests/filetests/parser/instruction_encoding.clif
View File

@@ -8,7 +8,7 @@ function %foo(i32, i32) {
ebb1(v0: i32 [%x8], v1: i32):
[-,-] v2 = iadd v0, v1
[-] trap heap_oob
[R#1234, %x5, %x11] v6, v7 = iadd_cout v2, v0
[R#1234, %x5, %x11] v6, v7 = iadd_ifcout v2, v0
[Rshamt#beef, %x25] v8 = ishl_imm v6, 2
@55 v9 = iadd v8, v7
@a5 [Iret#5] return v0, v8
@@ -17,7 +17,7 @@ ebb1(v0: i32 [%x8], v1: i32):
; nextln: ebb1(v0: i32 [%x8], v1: i32):
; nextln: [-,-]$WS v2 = iadd v0, v1
; nextln: [-]$WS trap heap_oob
; nextln: [R#1234,%x5,%x11]$WS v6, v7 = iadd_cout v2, v0
; nextln: [R#1234,%x5,%x11]$WS v6, v7 = iadd_ifcout v2, v0
; nextln: [Rshamt#beef,%x25]$WS v8 = ishl_imm v6, 2
; nextln: @0055 [-,-]$WS v9 = iadd v8, v7
; nextln: @00a5 [Iret#05]$WS return v0, v8

24
cranelift/filetests/filetests/parser/ternary.clif
View File

@@ -3,22 +3,22 @@ test verifier
function %add_i96(i32, i32, i32, i32, i32, i32) -> i32, i32, i32 {
ebb1(v1: i32, v2: i32, v3: i32, v4: i32, v5: i32, v6: i32):
v10, v11 = iadd_cout v1, v4
;check: v10, v11 = iadd_cout v1, v4
v20, v21 = iadd_carry v2, v5, v11
; check: v20, v21 = iadd_carry v2, v5, v11
v30 = iadd_cin v3, v6, v21
; check: v30 = iadd_cin v3, v6, v21
v10, v11 = iadd_ifcout v1, v4
;check: v10, v11 = iadd_ifcout v1, v4
v20, v21 = iadd_ifcarry v2, v5, v11
; check: v20, v21 = iadd_ifcarry v2, v5, v11
v30 = iadd_ifcin v3, v6, v21
; check: v30 = iadd_ifcin v3, v6, v21
return v10, v20, v30
}
function %sub_i96(i32, i32, i32, i32, i32, i32) -> i32, i32, i32 {
ebb1(v1: i32, v2: i32, v3: i32, v4: i32, v5: i32, v6: i32):
v10, v11 = isub_bout v1, v4
;check: v10, v11 = isub_bout v1, v4
v20, v21 = isub_borrow v2, v5, v11
; check: v20, v21 = isub_borrow v2, v5, v11
v30 = isub_bin v3, v6, v21
; check: v30 = isub_bin v3, v6, v21
v10, v11 = isub_ifbout v1, v4
;check: v10, v11 = isub_ifbout v1, v4
v20, v21 = isub_ifborrow v2, v5, v11
; check: v20, v21 = isub_ifborrow v2, v5, v11
v30 = isub_ifbin v3, v6, v21
; check: v30 = isub_ifbin v3, v6, v21
return v10, v20, v30
}