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[codegen] reintroduce support for carry and borrow instructions in RI… (#1005)

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Reintroduce support for iadd carry variants and isub borrow variants for
RISC ISAs which had been removed in
https://github.com/CraneStation/cranelift/pull/961 and
https://github.com/CraneStation/cranelift/pull/962 because of the lack
of a proper flags register in RISC architectures.
This commit is contained in:
Ujjwal Sharma
2019-09-13 20:57:50 +05:30
committed by Benjamin Bouvier
parent cadd0ac655
commit 3418fb6e18
17 changed files with 326 additions and 85 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
cranelift/codegen/meta/src/isa/arm32/mod.rs
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@@ -66,9 +66,9 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
let mut t32 = CpuMode::new("T32");
// TODO refine these.
let narrow = shared_defs.transform_groups.by_name("narrow");
a32.legalize_default(narrow);
t32.legalize_default(narrow);
let narrow_flags = shared_defs.transform_groups.by_name("narrow_flags");
a32.legalize_default(narrow_flags);
t32.legalize_default(narrow_flags);
let cpu_modes = vec![a32, t32];

4
cranelift/codegen/meta/src/isa/arm64/mod.rs
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@@ -60,8 +60,8 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
let mut a64 = CpuMode::new("A64");
// TODO refine these.
let narrow = shared_defs.transform_groups.by_name("narrow");
a64.legalize_default(narrow);
let narrow_flags = shared_defs.transform_groups.by_name("narrow_flags");
a64.legalize_default(narrow_flags);
let cpu_modes = vec![a64];

7
cranelift/codegen/meta/src/isa/riscv/mod.rs
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@@ -102,15 +102,16 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
let mut rv_64 = CpuMode::new("RV64");
let expand = shared_defs.transform_groups.by_name("expand");
let narrow = shared_defs.transform_groups.by_name("narrow");
let narrow_no_flags = shared_defs.transform_groups.by_name("narrow_no_flags");
rv_32.legalize_monomorphic(expand);
rv_32.legalize_default(narrow);
rv_32.legalize_default(narrow_no_flags);
rv_32.legalize_type(I32, expand);
rv_32.legalize_type(F32, expand);
rv_32.legalize_type(F64, expand);
rv_64.legalize_monomorphic(expand);
rv_64.legalize_default(narrow);
rv_64.legalize_default(narrow_no_flags);
rv_64.legalize_type(I32, expand);
rv_64.legalize_type(I64, expand);
rv_64.legalize_type(F32, expand);

24
cranelift/codegen/meta/src/isa/x86/encodings.rs
View File

@@ -384,9 +384,9 @@ pub(crate) fn define(
let func_addr = shared.by_name("func_addr");
let get_pinned_reg = shared.by_name("get_pinned_reg");
let iadd = shared.by_name("iadd");
let iadd_cout = shared.by_name("iadd_cout");
let iadd_cin = shared.by_name("iadd_cin");
let iadd_carry = shared.by_name("iadd_carry");
let iadd_ifcout = shared.by_name("iadd_ifcout");
let iadd_ifcin = shared.by_name("iadd_ifcin");
let iadd_ifcarry = shared.by_name("iadd_ifcarry");
let iadd_imm = shared.by_name("iadd_imm");
let icmp = shared.by_name("icmp");
let icmp_imm = shared.by_name("icmp_imm");
@@ -407,9 +407,9 @@ pub(crate) fn define(
let istore8 = shared.by_name("istore8");
let istore8_complex = shared.by_name("istore8_complex");
let isub = shared.by_name("isub");
let isub_bout = shared.by_name("isub_bout");
let isub_bin = shared.by_name("isub_bin");
let isub_borrow = shared.by_name("isub_borrow");
let isub_ifbout = shared.by_name("isub_ifbout");
let isub_ifbin = shared.by_name("isub_ifbin");
let isub_ifborrow = shared.by_name("isub_ifborrow");
let jump = shared.by_name("jump");
let jump_table_base = shared.by_name("jump_table_base");
let jump_table_entry = shared.by_name("jump_table_entry");
@@ -647,14 +647,14 @@ pub(crate) fn define(
);
e.enc_i32_i64(iadd, rec_rr.opcodes(vec![0x01]));
e.enc_i32_i64(iadd_cout, rec_rout.opcodes(vec![0x01]));
e.enc_i32_i64(iadd_cin, rec_rin.opcodes(vec![0x11]));
e.enc_i32_i64(iadd_carry, rec_rio.opcodes(vec![0x11]));
e.enc_i32_i64(iadd_ifcout, rec_rout.opcodes(vec![0x01]));
e.enc_i32_i64(iadd_ifcin, rec_rin.opcodes(vec![0x11]));
e.enc_i32_i64(iadd_ifcarry, rec_rio.opcodes(vec![0x11]));
e.enc_i32_i64(isub, rec_rr.opcodes(vec![0x29]));
e.enc_i32_i64(isub_bout, rec_rout.opcodes(vec![0x29]));
e.enc_i32_i64(isub_bin, rec_rin.opcodes(vec![0x19]));
e.enc_i32_i64(isub_borrow, rec_rio.opcodes(vec![0x19]));
e.enc_i32_i64(isub_ifbout, rec_rout.opcodes(vec![0x29]));
e.enc_i32_i64(isub_ifbin, rec_rin.opcodes(vec![0x19]));
e.enc_i32_i64(isub_ifborrow, rec_rio.opcodes(vec![0x19]));
e.enc_i32_i64(band, rec_rr.opcodes(vec![0x21]));
e.enc_i32_i64(bor, rec_rr.opcodes(vec![0x09]));

2
cranelift/codegen/meta/src/isa/x86/legalize.rs
View File

@@ -305,7 +305,7 @@ pub(crate) fn define(shared: &mut SharedDefinitions, x86_instructions: &Instruct
Use x86-specific instructions if needed."#,
)
.isa("x86")
.chain_with(shared.transform_groups.by_name("narrow").id);
.chain_with(shared.transform_groups.by_name("narrow_flags").id);
// SIMD
let uimm8_zero = Literal::constant(&imm.uimm8, 0x00);

4
cranelift/codegen/meta/src/isa/x86/mod.rs
View File

@@ -29,13 +29,13 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
let mut x86_32 = CpuMode::new("I32");
let expand_flags = shared_defs.transform_groups.by_name("expand_flags");
let narrow = shared_defs.transform_groups.by_name("narrow");
let narrow_flags = shared_defs.transform_groups.by_name("narrow_flags");
let widen = shared_defs.transform_groups.by_name("widen");
let x86_narrow = shared_defs.transform_groups.by_name("x86_narrow");
let x86_expand = shared_defs.transform_groups.by_name("x86_expand");
x86_32.legalize_monomorphic(expand_flags);
x86_32.legalize_default(narrow);
x86_32.legalize_default(narrow_flags);
x86_32.legalize_type(B1, expand_flags);
x86_32.legalize_type(I8, widen);
x86_32.legalize_type(I16, widen);