Enable the simd_i32x4_trunc_sat_f64x2 test for AArch64
Also, reorganize the AArch64-specific VCode instructions for unary narrowing and widening vector operations, so that they are more straightforward to use. Copyright (c) 2021, Arm Limited.
This commit is contained in:
Anton Kirilov
@@ -332,8 +332,6 @@ pub enum VecMisc2 {
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Fsqrt,
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/// Reverse elements in 64-bit doublewords
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Rev64,
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/// Shift left long (by element size)
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Shll,
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/// Floating-point convert to signed integer, rounding toward zero
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Fcvtzs,
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/// Floating-point convert to unsigned integer, rounding toward zero
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@@ -356,15 +354,48 @@ pub enum VecMisc2 {
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Cmeq0,
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}
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/// A Vector narrowing operation with two registers.
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/// A vector widening operation with one argument.
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#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
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pub enum VecMiscNarrowOp {
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/// Extract Narrow
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Xtn,
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/// Signed saturating extract narrow
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Sqxtn,
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/// Signed saturating extract unsigned narrow
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Sqxtun,
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pub enum VecRRLongOp {
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/// Floating-point convert to higher precision long, 16-bit elements
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Fcvtl16,
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/// Floating-point convert to higher precision long, 32-bit elements
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Fcvtl32,
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/// Shift left long (by element size), 8-bit elements
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Shll8,
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/// Shift left long (by element size), 16-bit elements
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Shll16,
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/// Shift left long (by element size), 32-bit elements
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Shll32,
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}
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/// A vector narrowing operation with one argument.
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#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
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pub enum VecRRNarrowOp {
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/// Extract narrow, 16-bit elements
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Xtn16,
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/// Extract narrow, 32-bit elements
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Xtn32,
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/// Extract narrow, 64-bit elements
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Xtn64,
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/// Signed saturating extract narrow, 16-bit elements
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Sqxtn16,
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/// Signed saturating extract narrow, 32-bit elements
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Sqxtn32,
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/// Signed saturating extract narrow, 64-bit elements
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Sqxtn64,
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/// Signed saturating extract unsigned narrow, 16-bit elements
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Sqxtun16,
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/// Signed saturating extract unsigned narrow, 32-bit elements
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Sqxtun32,
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/// Signed saturating extract unsigned narrow, 64-bit elements
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Sqxtun64,
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/// Unsigned saturating extract narrow, 16-bit elements
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Uqxtn16,
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/// Unsigned saturating extract narrow, 32-bit elements
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Uqxtn32,
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/// Unsigned saturating extract narrow, 64-bit elements
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Uqxtn64,
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}
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/// A vector operation on a pair of elements with one register.
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@@ -1029,12 +1060,19 @@ pub enum Inst {
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size: VectorSize,
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},
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/// Vector narrowing operation.
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VecMiscNarrow {
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op: VecMiscNarrowOp,
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/// Vector widening operation.
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VecRRLong {
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op: VecRRLongOp,
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rd: Writable<Reg>,
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rn: Reg,
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high_half: bool,
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},
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/// Vector narrowing operation.
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VecRRNarrow {
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op: VecRRNarrowOp,
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rd: Writable<Reg>,
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rn: Reg,
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size: VectorSize,
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high_half: bool,
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},
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@@ -2073,7 +2111,11 @@ fn aarch64_get_regs(inst: &Inst, collector: &mut RegUsageCollector) {
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collector.add_mod(rd);
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collector.add_use(rn);
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}
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&Inst::VecMiscNarrow {
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&Inst::VecRRLong { rd, rn, .. } => {
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collector.add_def(rd);
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collector.add_use(rn);
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}
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&Inst::VecRRNarrow {
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rd, rn, high_half, ..
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} => {
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collector.add_use(rn);
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@@ -2868,7 +2910,15 @@ fn aarch64_map_regs<RUM: RegUsageMapper>(inst: &mut Inst, mapper: &RUM) {
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map_mod(mapper, rd);
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map_use(mapper, rn);
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}
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&mut Inst::VecMiscNarrow {
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&mut Inst::VecRRLong {
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ref mut rd,
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ref mut rn,
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..
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} => {
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map_def(mapper, rd);
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map_use(mapper, rn);
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}
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&mut Inst::VecRRNarrow {
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ref mut rd,
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ref mut rn,
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high_half,
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@@ -3901,29 +3951,132 @@ impl Inst {
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let rn = show_vreg_element(rn, mb_rru, src_idx, size);
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format!("mov {}, {}", rd, rn)
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}
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&Inst::VecMiscNarrow {
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&Inst::VecRRLong {
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op,
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rd,
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rn,
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size,
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high_half,
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} => {
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let dest_size = if high_half {
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assert!(size.is_128bits());
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size
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} else {
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size.halve()
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let (op, rd_size, size, suffix) = match (op, high_half) {
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(VecRRLongOp::Fcvtl16, false) => {
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("fcvtl", VectorSize::Size32x4, VectorSize::Size16x4, "")
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}
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(VecRRLongOp::Fcvtl16, true) => {
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("fcvtl2", VectorSize::Size32x4, VectorSize::Size16x8, "")
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}
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(VecRRLongOp::Fcvtl32, false) => {
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("fcvtl", VectorSize::Size64x2, VectorSize::Size32x2, "")
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}
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(VecRRLongOp::Fcvtl32, true) => {
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("fcvtl2", VectorSize::Size64x2, VectorSize::Size32x4, "")
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}
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(VecRRLongOp::Shll8, false) => {
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("shll", VectorSize::Size16x8, VectorSize::Size8x8, ", #8")
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}
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(VecRRLongOp::Shll8, true) => {
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("shll2", VectorSize::Size16x8, VectorSize::Size8x16, ", #8")
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}
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(VecRRLongOp::Shll16, false) => {
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("shll", VectorSize::Size32x4, VectorSize::Size16x4, ", #16")
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}
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(VecRRLongOp::Shll16, true) => {
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("shll2", VectorSize::Size32x4, VectorSize::Size16x8, ", #16")
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}
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(VecRRLongOp::Shll32, false) => {
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("shll", VectorSize::Size64x2, VectorSize::Size32x2, ", #32")
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}
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(VecRRLongOp::Shll32, true) => {
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("shll2", VectorSize::Size64x2, VectorSize::Size32x4, ", #32")
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}
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};
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let rd = show_vreg_vector(rd.to_reg(), mb_rru, dest_size);
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let rn = show_vreg_vector(rn, mb_rru, size.widen());
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let op = match (op, high_half) {
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(VecMiscNarrowOp::Xtn, false) => "xtn",
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(VecMiscNarrowOp::Xtn, true) => "xtn2",
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(VecMiscNarrowOp::Sqxtn, false) => "sqxtn",
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(VecMiscNarrowOp::Sqxtn, true) => "sqxtn2",
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(VecMiscNarrowOp::Sqxtun, false) => "sqxtun",
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(VecMiscNarrowOp::Sqxtun, true) => "sqxtun2",
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let rd = show_vreg_vector(rd.to_reg(), mb_rru, rd_size);
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let rn = show_vreg_vector(rn, mb_rru, size);
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format!("{} {}, {}{}", op, rd, rn, suffix)
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}
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&Inst::VecRRNarrow {
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op,
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rd,
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rn,
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high_half,
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} => {
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let (op, rd_size, size) = match (op, high_half) {
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(VecRRNarrowOp::Xtn16, false) => {
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("xtn", VectorSize::Size8x8, VectorSize::Size16x8)
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}
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(VecRRNarrowOp::Xtn16, true) => {
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("xtn2", VectorSize::Size8x16, VectorSize::Size16x8)
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}
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(VecRRNarrowOp::Xtn32, false) => {
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("xtn", VectorSize::Size16x4, VectorSize::Size32x4)
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}
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(VecRRNarrowOp::Xtn32, true) => {
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("xtn2", VectorSize::Size16x8, VectorSize::Size32x4)
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}
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(VecRRNarrowOp::Xtn64, false) => {
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("xtn", VectorSize::Size32x2, VectorSize::Size64x2)
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}
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(VecRRNarrowOp::Xtn64, true) => {
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("xtn2", VectorSize::Size32x4, VectorSize::Size64x2)
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}
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(VecRRNarrowOp::Sqxtn16, false) => {
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("sqxtn", VectorSize::Size8x8, VectorSize::Size16x8)
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}
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(VecRRNarrowOp::Sqxtn16, true) => {
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("sqxtn2", VectorSize::Size8x16, VectorSize::Size16x8)
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}
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(VecRRNarrowOp::Sqxtn32, false) => {
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("sqxtn", VectorSize::Size16x4, VectorSize::Size32x4)
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}
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(VecRRNarrowOp::Sqxtn32, true) => {
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("sqxtn2", VectorSize::Size16x8, VectorSize::Size32x4)
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}
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(VecRRNarrowOp::Sqxtn64, false) => {
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("sqxtn", VectorSize::Size32x2, VectorSize::Size64x2)
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}
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(VecRRNarrowOp::Sqxtn64, true) => {
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("sqxtn2", VectorSize::Size32x4, VectorSize::Size64x2)
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}
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(VecRRNarrowOp::Sqxtun16, false) => {
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("sqxtun", VectorSize::Size8x8, VectorSize::Size16x8)
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}
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(VecRRNarrowOp::Sqxtun16, true) => {
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("sqxtun2", VectorSize::Size8x16, VectorSize::Size16x8)
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}
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(VecRRNarrowOp::Sqxtun32, false) => {
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("sqxtun", VectorSize::Size16x4, VectorSize::Size32x4)
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}
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(VecRRNarrowOp::Sqxtun32, true) => {
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("sqxtun2", VectorSize::Size16x8, VectorSize::Size32x4)
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}
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(VecRRNarrowOp::Sqxtun64, false) => {
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("sqxtun", VectorSize::Size32x2, VectorSize::Size64x2)
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}
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(VecRRNarrowOp::Sqxtun64, true) => {
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("sqxtun2", VectorSize::Size32x4, VectorSize::Size64x2)
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}
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(VecRRNarrowOp::Uqxtn16, false) => {
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("uqxtn", VectorSize::Size8x8, VectorSize::Size16x8)
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}
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(VecRRNarrowOp::Uqxtn16, true) => {
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("uqxtn2", VectorSize::Size8x16, VectorSize::Size16x8)
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}
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(VecRRNarrowOp::Uqxtn32, false) => {
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("uqxtn", VectorSize::Size16x4, VectorSize::Size32x4)
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}
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(VecRRNarrowOp::Uqxtn32, true) => {
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("uqxtn2", VectorSize::Size16x8, VectorSize::Size32x4)
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}
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(VecRRNarrowOp::Uqxtn64, false) => {
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("uqxtn", VectorSize::Size32x2, VectorSize::Size64x2)
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}
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(VecRRNarrowOp::Uqxtn64, true) => {
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("uqxtn2", VectorSize::Size32x4, VectorSize::Size64x2)
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}
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};
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let rd = show_vreg_vector(rd.to_reg(), mb_rru, rd_size);
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let rn = show_vreg_vector(rn, mb_rru, size);
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format!("{} {}, {}", op, rd, rn)
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}
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&Inst::VecRRPair { op, rd, rn } => {
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@@ -3999,45 +4152,34 @@ impl Inst {
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format!("{} {}, {}, {}", op, rd, rn, rm)
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}
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&Inst::VecMisc { op, rd, rn, size } => {
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let (op, rd_size, size, suffix) = match op {
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VecMisc2::Not => {
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let size = if size.is_128bits() {
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let (op, size, suffix) = match op {
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VecMisc2::Not => (
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"mvn",
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if size.is_128bits() {
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VectorSize::Size8x16
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} else {
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VectorSize::Size8x8
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};
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("mvn", size, size, "")
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}
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VecMisc2::Neg => ("neg", size, size, ""),
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VecMisc2::Abs => ("abs", size, size, ""),
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VecMisc2::Fabs => ("fabs", size, size, ""),
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VecMisc2::Fneg => ("fneg", size, size, ""),
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VecMisc2::Fsqrt => ("fsqrt", size, size, ""),
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VecMisc2::Rev64 => ("rev64", size, size, ""),
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VecMisc2::Shll => (
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"shll",
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size.widen(),
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size,
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match size {
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VectorSize::Size8x8 => ", #8",
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VectorSize::Size16x4 => ", #16",
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VectorSize::Size32x2 => ", #32",
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_ => panic!("Unexpected vector size: {:?}", size),
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},
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"",
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),
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VecMisc2::Fcvtzs => ("fcvtzs", size, size, ""),
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VecMisc2::Fcvtzu => ("fcvtzu", size, size, ""),
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VecMisc2::Scvtf => ("scvtf", size, size, ""),
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VecMisc2::Ucvtf => ("ucvtf", size, size, ""),
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VecMisc2::Frintn => ("frintn", size, size, ""),
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VecMisc2::Frintz => ("frintz", size, size, ""),
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VecMisc2::Frintm => ("frintm", size, size, ""),
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VecMisc2::Frintp => ("frintp", size, size, ""),
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VecMisc2::Cnt => ("cnt", size, size, ""),
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VecMisc2::Cmeq0 => ("cmeq", size, size, ", #0"),
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VecMisc2::Neg => ("neg", size, ""),
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VecMisc2::Abs => ("abs", size, ""),
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VecMisc2::Fabs => ("fabs", size, ""),
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VecMisc2::Fneg => ("fneg", size, ""),
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VecMisc2::Fsqrt => ("fsqrt", size, ""),
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VecMisc2::Rev64 => ("rev64", size, ""),
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VecMisc2::Fcvtzs => ("fcvtzs", size, ""),
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VecMisc2::Fcvtzu => ("fcvtzu", size, ""),
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VecMisc2::Scvtf => ("scvtf", size, ""),
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VecMisc2::Ucvtf => ("ucvtf", size, ""),
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VecMisc2::Frintn => ("frintn", size, ""),
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VecMisc2::Frintz => ("frintz", size, ""),
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VecMisc2::Frintm => ("frintm", size, ""),
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VecMisc2::Frintp => ("frintp", size, ""),
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VecMisc2::Cnt => ("cnt", size, ""),
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VecMisc2::Cmeq0 => ("cmeq", size, ", #0"),
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};
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let rd = show_vreg_vector(rd.to_reg(), mb_rru, rd_size);
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let rd = show_vreg_vector(rd.to_reg(), mb_rru, size);
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let rn = show_vreg_vector(rn, mb_rru, size);
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format!("{} {}, {}{}", op, rd, rn, suffix)
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}
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