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Enable the simd_i32x4_trunc_sat_f64x2 test for AArch64

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Also, reorganize the AArch64-specific VCode instructions for unary
narrowing and widening vector operations, so that they are more
straightforward to use.

Copyright (c) 2021, Arm Limited.
This commit is contained in:
Anton Kirilov
2021-06-28 19:22:57 +01:00
parent c5609bc364
commit 330f02aa09
11 changed files with 492 additions and 161 deletions
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35
cranelift/codegen/meta/src/shared/instructions.rs
View File

@@ -3985,19 +3985,19 @@ pub(crate) fn define(
.constraints(vec![WiderOrEq(Int.clone(), IntTo.clone())]),
);
let I16or32xN = &TypeVar::new(
"I16or32xN",
"A SIMD vector type containing integer lanes 16 or 32 bits wide",
let I16or32or64xN = &TypeVar::new(
"I16or32or64xN",
"A SIMD vector type containing integer lanes 16, 32, or 64 bits wide",
TypeSetBuilder::new()
.ints(16..32)
.simd_lanes(4..8)
.ints(16..64)
.simd_lanes(2..8)
.includes_scalars(false)
.build(),
);
let x = &Operand::new("x", I16or32xN);
let y = &Operand::new("y", I16or32xN);
let a = &Operand::new("a", &I16or32xN.split_lanes());
let x = &Operand::new("x", I16or32or64xN);
let y = &Operand::new("y", I16or32or64xN);
let a = &Operand::new("a", &I16or32or64xN.split_lanes());
ig.push(
Inst::new(
@@ -4036,6 +4036,25 @@ pub(crate) fn define(
.operands_out(vec![a]),
);
ig.push(
Inst::new(
"uunarrow",
r#"
Combine `x` and `y` into a vector with twice the lanes but half the integer width while
saturating overflowing values to the unsigned maximum and minimum.
Note that all input lanes are considered unsigned.
The lanes will be concatenated after narrowing. For example, when `x` and `y` are `i32x4`
and `x = [x3, x2, x1, x0]` and `y = [y3, y2, y1, y0]`, then after narrowing the value
returned is an `i16x8`: `a = [y3', y2', y1', y0', x3', x2', x1', x0']`.
"#,
&formats.binary,
)
.operands_in(vec![x, y])
.operands_out(vec![a]),
);
let I8or16or32xN = &TypeVar::new(
"I8or16or32xN",
"A SIMD vector type containing integer lanes 8, 16, or 32 bits wide.",