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fix codegen riscv64 normalize_cmp_value. (#5873)

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* fix issue5839

* add target.

* fix normalize_cmp_value.

* fix test failutre.

* fix test failure.

* fix parameter type.

* Update cranelift/codegen/src/isa/riscv64/inst.isle

Co-authored-by: Jamey Sharp <jamey@minilop.net>

* Update cranelift/codegen/src/isa/riscv64/lower.isle

Co-authored-by: Jamey Sharp <jamey@minilop.net>

* remove convert rule from IntCC to ExtendOp

---------

Co-authored-by: Jamey Sharp <jamey@minilop.net>
This commit is contained in:
yuyang
2023-03-01 07:00:23 +08:00
committed by GitHub
parent 0e9a48afd5
commit 32cfd60877
9 changed files with 109 additions and 66 deletions
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17
cranelift/codegen/src/isa/riscv64/lower/isle.rs
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@@ -3,7 +3,7 @@
// Pull in the ISLE generated code.
#[allow(unused)]
pub mod generated_code;
use generated_code::{Context, MInst};
use generated_code::{Context, ExtendOp, MInst};
// Types that the generated ISLE code uses via `use super::*`.
use super::{writable_zero_reg, zero_reg};
@@ -60,7 +60,22 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
_ => unreachable!(),
}
}
fn intcc_to_extend_op(&mut self, cc: &IntCC) -> ExtendOp {
use IntCC::*;
match *cc {
Equal
| NotEqual
| UnsignedLessThan
| UnsignedGreaterThanOrEqual
| UnsignedGreaterThan
| UnsignedLessThanOrEqual => ExtendOp::Zero,
SignedLessThan
| SignedGreaterThanOrEqual
| SignedGreaterThan
| SignedLessThanOrEqual => ExtendOp::Signed,
}
}
fn lower_cond_br(
&mut self,
cc: &IntCC,