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cranelift: Remove booleans (#5031)

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Remove the boolean types from cranelift, and the associated instructions breduce, bextend, bconst, and bint. Standardize on using 1/0 for the return value from instructions that produce scalar boolean results, and -1/0 for boolean vector elements.

Fixes #3205

Co-authored-by: Afonso Bordado <afonso360@users.noreply.github.com>
Co-authored-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
Co-authored-by: Chris Fallin <chris@cfallin.org>
This commit is contained in:
Trevor Elliott
2022-10-17 16:00:27 -07:00
committed by GitHub
parent 766ecb561e
commit 32a7593c94
242 changed files with 7695 additions and 10010 deletions
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6
cranelift/filetests/filetests/isa/aarch64/atomic-cas.clif
View File

@@ -7,8 +7,7 @@ function u0:0(i64, i32, i32) -> i8 system_v {
block0(v0: i64, v1: i32, v2: i32):
v6 = atomic_cas.i32 v0, v1, v2
v7 = icmp eq v6, v1
v8 = bint.i8 v7
return v8
return v7
}
; stp fp, lr, [sp, #-16]!
@@ -22,8 +21,7 @@ block0(v0: i64, v1: i32, v2: i32):
; mov x28, x2
; atomic_cas_loop_32 addr=x25, expect=x26, replacement=x28, oldval=x27, scratch=x24
; subs wzr, w27, w26
; cset x8, eq
; and w0, w8, #1
; cset x0, eq
; ldp x24, x25, [sp], #16
; ldp x26, x27, [sp], #16
; ldr x28, [sp], #16

18
cranelift/filetests/filetests/isa/aarch64/bitops.clif
View File

@@ -304,28 +304,28 @@ block0(v0: i8):
; umov w0, v5.b[0]
; ret
function %bextend_b8() -> b32 {
function %sextend_i8() -> i32 {
block0:
v1 = bconst.b8 true
v2 = bextend.b32 v1
v1 = iconst.i8 -1
v2 = sextend.i32 v1
return v2
}
; block0:
; movz x1, #255
; movn x1, #0
; sxtb w0, w1
; ret
function %bextend_b1() -> b32 {
function %sextend_i8() -> i32 {
block0:
v1 = bconst.b1 true
v2 = bextend.b32 v1
v1 = iconst.i8 -1
v2 = sextend.i32 v1
return v2
}
; block0:
; movz x1, #1
; sbfx w0, w1, #0, #1
; movn x1, #0
; sxtb w0, w1
; ret
function %bnot_i32(i32) -> i32 {

96
cranelift/filetests/filetests/isa/aarch64/compare_zero.clif
View File

@@ -2,7 +2,7 @@ test compile precise-output
set unwind_info=false
target aarch64
function %f0(i8x16) -> b8x16 {
function %f0(i8x16) -> i8x16 {
block0(v0: i8x16):
v1 = iconst.i8 0
v2 = splat.i8x16 v1
@@ -14,7 +14,7 @@ block0(v0: i8x16):
; cmeq v0.16b, v0.16b, #0
; ret
function %f0_vconst(i8x16) -> b8x16 {
function %f0_vconst(i8x16) -> i8x16 {
block0(v0: i8x16):
v1 = vconst.i8x16 0x00
v2 = icmp eq v0, v1
@@ -25,7 +25,7 @@ block0(v0: i8x16):
; cmeq v0.16b, v0.16b, #0
; ret
function %f1(i16x8) -> b16x8 {
function %f1(i16x8) -> i16x8 {
block0(v0: i16x8):
v1 = iconst.i16 0
v2 = splat.i16x8 v1
@@ -37,7 +37,7 @@ block0(v0: i16x8):
; cmeq v0.8h, v0.8h, #0
; ret
function %f1_vconst(i16x8) -> b16x8 {
function %f1_vconst(i16x8) -> i16x8 {
block0(v0: i16x8):
v1 = vconst.i16x8 0x00
v2 = icmp eq v1, v0
@@ -48,7 +48,7 @@ block0(v0: i16x8):
; cmeq v0.8h, v0.8h, #0
; ret
function %f2(i32x4) -> b32x4 {
function %f2(i32x4) -> i32x4 {
block0(v0: i32x4):
v1 = iconst.i32 0
v2 = splat.i32x4 v1
@@ -61,7 +61,7 @@ block0(v0: i32x4):
; mvn v0.16b, v3.16b
; ret
function %f2_vconst(i32x4) -> b32x4 {
function %f2_vconst(i32x4) -> i32x4 {
block0(v0: i32x4):
v1 = vconst.i32x4 0x00
v2 = icmp ne v0, v1
@@ -73,7 +73,7 @@ block0(v0: i32x4):
; mvn v0.16b, v3.16b
; ret
function %f3(i64x2) -> b64x2 {
function %f3(i64x2) -> i64x2 {
block0(v0: i64x2):
v1 = iconst.i64 0
v2 = splat.i64x2 v1
@@ -86,7 +86,7 @@ block0(v0: i64x2):
; mvn v0.16b, v3.16b
; ret
function %f3_vconst(i64x2) -> b64x2 {
function %f3_vconst(i64x2) -> i64x2 {
block0(v0: i64x2):
v1 = vconst.i64x2 0x00
v2 = icmp ne v1, v0
@@ -98,7 +98,7 @@ block0(v0: i64x2):
; mvn v0.16b, v3.16b
; ret
function %f4(i8x16) -> b8x16 {
function %f4(i8x16) -> i8x16 {
block0(v0: i8x16):
v1 = iconst.i8 0
v2 = splat.i8x16 v1
@@ -110,7 +110,7 @@ block0(v0: i8x16):
; cmle v0.16b, v0.16b, #0
; ret
function %f4_vconst(i8x16) -> b8x16 {
function %f4_vconst(i8x16) -> i8x16 {
block0(v0: i8x16):
v1 = vconst.i8x16 0x00
v2 = icmp sle v0, v1
@@ -121,7 +121,7 @@ block0(v0: i8x16):
; cmle v0.16b, v0.16b, #0
; ret
function %f5(i16x8) -> b16x8 {
function %f5(i16x8) -> i16x8 {
block0(v0: i16x8):
v1 = iconst.i16 0
v2 = splat.i16x8 v1
@@ -133,7 +133,7 @@ block0(v0: i16x8):
; cmge v0.8h, v0.8h, #0
; ret
function %f5_vconst(i16x8) -> b16x8 {
function %f5_vconst(i16x8) -> i16x8 {
block0(v0: i16x8):
v1 = vconst.i16x8 0x00
v2 = icmp sle v1, v0
@@ -144,7 +144,7 @@ block0(v0: i16x8):
; cmge v0.8h, v0.8h, #0
; ret
function %f6(i32x4) -> b32x4 {
function %f6(i32x4) -> i32x4 {
block0(v0: i32x4):
v1 = iconst.i32 0
v2 = splat.i32x4 v1
@@ -156,7 +156,7 @@ block0(v0: i32x4):
; cmge v0.4s, v0.4s, #0
; ret
function %f6_vconst(i32x4) -> b32x4 {
function %f6_vconst(i32x4) -> i32x4 {
block0(v0: i32x4):
v1 = vconst.i32x4 0x00
v2 = icmp sge v0, v1
@@ -167,7 +167,7 @@ block0(v0: i32x4):
; cmge v0.4s, v0.4s, #0
; ret
function %f7(i64x2) -> b64x2 {
function %f7(i64x2) -> i64x2 {
block0(v0: i64x2):
v1 = iconst.i64 0
v2 = splat.i64x2 v1
@@ -179,7 +179,7 @@ block0(v0: i64x2):
; cmle v0.2d, v0.2d, #0
; ret
function %f7_vconst(i64x2) -> b64x2 {
function %f7_vconst(i64x2) -> i64x2 {
block0(v0: i64x2):
v1 = vconst.i64x2 0x00
v2 = icmp sge v1, v0
@@ -190,7 +190,7 @@ block0(v0: i64x2):
; cmle v0.2d, v0.2d, #0
; ret
function %f8(i8x16) -> b8x16 {
function %f8(i8x16) -> i8x16 {
block0(v0: i8x16):
v1 = iconst.i8 0
v2 = splat.i8x16 v1
@@ -202,7 +202,7 @@ block0(v0: i8x16):
; cmlt v0.16b, v0.16b, #0
; ret
function %f8_vconst(i8x16) -> b8x16 {
function %f8_vconst(i8x16) -> i8x16 {
block0(v0: i8x16):
v1 = vconst.i8x16 0x00
v2 = icmp slt v0, v1
@@ -213,7 +213,7 @@ block0(v0: i8x16):
; cmlt v0.16b, v0.16b, #0
; ret
function %f9(i16x8) -> b16x8 {
function %f9(i16x8) -> i16x8 {
block0(v0: i16x8):
v1 = iconst.i16 0
v2 = splat.i16x8 v1
@@ -225,7 +225,7 @@ block0(v0: i16x8):
; cmgt v0.8h, v0.8h, #0
; ret
function %f9_vconst(i16x8) -> b16x8 {
function %f9_vconst(i16x8) -> i16x8 {
block0(v0: i16x8):
v1 = vconst.i16x8 0x00
v2 = icmp slt v1, v0
@@ -236,7 +236,7 @@ block0(v0: i16x8):
; cmgt v0.8h, v0.8h, #0
; ret
function %f10(i32x4) -> b32x4 {
function %f10(i32x4) -> i32x4 {
block0(v0: i32x4):
v1 = iconst.i32 0
v2 = splat.i32x4 v1
@@ -248,7 +248,7 @@ block0(v0: i32x4):
; cmgt v0.4s, v0.4s, #0
; ret
function %f10_vconst(i32x4) -> b32x4 {
function %f10_vconst(i32x4) -> i32x4 {
block0(v0: i32x4):
v1 = vconst.i32x4 0x00
v2 = icmp sgt v0, v1
@@ -259,7 +259,7 @@ block0(v0: i32x4):
; cmgt v0.4s, v0.4s, #0
; ret
function %f11(i64x2) -> b64x2 {
function %f11(i64x2) -> i64x2 {
block0(v0: i64x2):
v1 = iconst.i64 0
v2 = splat.i64x2 v1
@@ -271,7 +271,7 @@ block0(v0: i64x2):
; cmlt v0.2d, v0.2d, #0
; ret
function %f11_vconst(i64x2) -> b64x2 {
function %f11_vconst(i64x2) -> i64x2 {
block0(v0: i64x2):
v1 = vconst.i64x2 0x00
v2 = icmp sgt v1, v0
@@ -282,7 +282,7 @@ block0(v0: i64x2):
; cmlt v0.2d, v0.2d, #0
; ret
function %f12(f32x4) -> b32x4 {
function %f12(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = f32const 0.0
v2 = splat.f32x4 v1
@@ -294,7 +294,7 @@ block0(v0: f32x4):
; fcmeq v0.4s, v0.4s, #0.0
; ret
function %f12_vconst(f32x4) -> b32x4 {
function %f12_vconst(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = vconst.f32x4 [0.0 0.0 0.0 0.0]
v2 = fcmp eq v0, v1
@@ -305,7 +305,7 @@ block0(v0: f32x4):
; fcmeq v0.4s, v0.4s, #0.0
; ret
function %f13(f64x2) -> b64x2 {
function %f13(f64x2) -> i64x2 {
block0(v0: f64x2):
v1 = f64const 0.0
v2 = splat.f64x2 v1
@@ -317,7 +317,7 @@ block0(v0: f64x2):
; fcmeq v0.2d, v0.2d, #0.0
; ret
function %f13_vconst(f64x2) -> b64x2 {
function %f13_vconst(f64x2) -> i64x2 {
block0(v0: f64x2):
v1 = vconst.f64x2 [0.0 0.0]
v2 = fcmp eq v1, v0
@@ -328,7 +328,7 @@ block0(v0: f64x2):
; fcmeq v0.2d, v0.2d, #0.0
; ret
function %f14(f64x2) -> b64x2 {
function %f14(f64x2) -> i64x2 {
block0(v0: f64x2):
v1 = f64const 0.0
v2 = splat.f64x2 v1
@@ -341,7 +341,7 @@ block0(v0: f64x2):
; mvn v0.16b, v3.16b
; ret
function %f14_vconst(f64x2) -> b64x2 {
function %f14_vconst(f64x2) -> i64x2 {
block0(v0: f64x2):
v1 = vconst.f64x2 [0.0 0.0]
v2 = fcmp ne v0, v1
@@ -353,7 +353,7 @@ block0(v0: f64x2):
; mvn v0.16b, v3.16b
; ret
function %f15(f32x4) -> b32x4 {
function %f15(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = f32const 0.0
v2 = splat.f32x4 v1
@@ -366,7 +366,7 @@ block0(v0: f32x4):
; mvn v0.16b, v3.16b
; ret
function %f15_vconst(f32x4) -> b32x4 {
function %f15_vconst(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = vconst.f32x4 [0.0 0.0 0.0 0.0]
v2 = fcmp ne v1, v0
@@ -378,7 +378,7 @@ block0(v0: f32x4):
; mvn v0.16b, v3.16b
; ret
function %f16(f32x4) -> b32x4 {
function %f16(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = f32const 0.0
v2 = splat.f32x4 v1
@@ -390,7 +390,7 @@ block0(v0: f32x4):
; fcmle v0.4s, v0.4s, #0.0
; ret
function %f16_vconst(f32x4) -> b32x4 {
function %f16_vconst(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = vconst.f32x4 [0.0 0.0 0.0 0.0]
v2 = fcmp le v0, v1
@@ -401,7 +401,7 @@ block0(v0: f32x4):
; fcmle v0.4s, v0.4s, #0.0
; ret
function %f17(f64x2) -> b64x2 {
function %f17(f64x2) -> i64x2 {
block0(v0: f64x2):
v1 = f64const 0.0
v2 = splat.f64x2 v1
@@ -413,7 +413,7 @@ block0(v0: f64x2):
; fcmge v0.2d, v0.2d, #0.0
; ret
function %f17_vconst(f64x2) -> b64x2 {
function %f17_vconst(f64x2) -> i64x2 {
block0(v0: f64x2):
v1 = vconst.f64x2 [0.0 0.0]
v2 = fcmp le v1, v0
@@ -424,7 +424,7 @@ block0(v0: f64x2):
; fcmge v0.2d, v0.2d, #0.0
; ret
function %f18(f64x2) -> b64x2 {
function %f18(f64x2) -> i64x2 {
block0(v0: f64x2):
v1 = f64const 0.0
v2 = splat.f64x2 v1
@@ -436,7 +436,7 @@ block0(v0: f64x2):
; fcmge v0.2d, v0.2d, #0.0
; ret
function %f18_vconst(f64x2) -> b64x2 {
function %f18_vconst(f64x2) -> i64x2 {
block0(v0: f64x2):
v1 = vconst.f64x2 [0.0 0.0]
v2 = fcmp ge v0, v1
@@ -447,7 +447,7 @@ block0(v0: f64x2):
; fcmge v0.2d, v0.2d, #0.0
; ret
function %f19(f32x4) -> b32x4 {
function %f19(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = f32const 0.0
v2 = splat.f32x4 v1
@@ -459,7 +459,7 @@ block0(v0: f32x4):
; fcmle v0.4s, v0.4s, #0.0
; ret
function %f19_vconst(f32x4) -> b32x4 {
function %f19_vconst(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = vconst.f32x4 [0.0 0.0 0.0 0.0]
v2 = fcmp ge v1, v0
@@ -470,7 +470,7 @@ block0(v0: f32x4):
; fcmle v0.4s, v0.4s, #0.0
; ret
function %f20(f32x4) -> b32x4 {
function %f20(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = f32const 0.0
v2 = splat.f32x4 v1
@@ -482,7 +482,7 @@ block0(v0: f32x4):
; fcmlt v0.4s, v0.4s, #0.0
; ret
function %f20_vconst(f32x4) -> b32x4 {
function %f20_vconst(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = vconst.f32x4 [0.0 0.0 0.0 0.0]
v2 = fcmp lt v0, v1
@@ -493,7 +493,7 @@ block0(v0: f32x4):
; fcmlt v0.4s, v0.4s, #0.0
; ret
function %f21(f64x2) -> b64x2 {
function %f21(f64x2) -> i64x2 {
block0(v0: f64x2):
v1 = f64const 0.0
v2 = splat.f64x2 v1
@@ -505,7 +505,7 @@ block0(v0: f64x2):
; fcmgt v0.2d, v0.2d, #0.0
; ret
function %f21_vconst(f64x2) -> b64x2 {
function %f21_vconst(f64x2) -> i64x2 {
block0(v0: f64x2):
v1 = vconst.f64x2 [0.0 0.0]
v2 = fcmp lt v1, v0
@@ -516,7 +516,7 @@ block0(v0: f64x2):
; fcmgt v0.2d, v0.2d, #0.0
; ret
function %f22(f64x2) -> b64x2 {
function %f22(f64x2) -> i64x2 {
block0(v0: f64x2):
v1 = f64const 0.0
v2 = splat.f64x2 v1
@@ -528,7 +528,7 @@ block0(v0: f64x2):
; fcmgt v0.2d, v0.2d, #0.0
; ret
function %f22_vconst(f64x2) -> b64x2 {
function %f22_vconst(f64x2) -> i64x2 {
block0(v0: f64x2):
v1 = vconst.f64x2 [0.0 0.0]
v2 = fcmp gt v0, v1
@@ -539,7 +539,7 @@ block0(v0: f64x2):
; fcmgt v0.2d, v0.2d, #0.0
; ret
function %f23(f32x4) -> b32x4 {
function %f23(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = f32const 0.0
v2 = splat.f32x4 v1
@@ -551,7 +551,7 @@ block0(v0: f32x4):
; fcmlt v0.4s, v0.4s, #0.0
; ret
function %f23_vconst(f32x4) -> b32x4 {
function %f23_vconst(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = vconst.f32x4 [0.0 0.0 0.0 0.0]
v2 = fcmp gt v1, v0

23
cranelift/filetests/filetests/isa/aarch64/condbr.clif
View File

@@ -2,7 +2,7 @@ test compile precise-output
set unwind_info=false
target aarch64
function %f(i64, i64) -> b1 {
function %f(i64, i64) -> i8 {
block0(v0: i64, v1: i64):
v2 = icmp eq v0, v1
return v2
@@ -13,7 +13,7 @@ block0(v0: i64, v1: i64):
; cset x0, eq
; ret
function %icmp_eq_i128(i128, i128) -> b1 {
function %icmp_eq_i128(i128, i128) -> i8 {
block0(v0: i128, v1: i128):
v2 = icmp eq v0, v1
return v2
@@ -25,7 +25,7 @@ block0(v0: i128, v1: i128):
; cset x0, eq
; ret
function %icmp_ne_i128(i128, i128) -> b1 {
function %icmp_ne_i128(i128, i128) -> i8 {
block0(v0: i128, v1: i128):
v2 = icmp ne v0, v1
return v2
@@ -37,7 +37,7 @@ block0(v0: i128, v1: i128):
; cset x0, ne
; ret
function %icmp_slt_i128(i128, i128) -> b1 {
function %icmp_slt_i128(i128, i128) -> i8 {
block0(v0: i128, v1: i128):
v2 = icmp slt v0, v1
return v2
@@ -51,7 +51,7 @@ block0(v0: i128, v1: i128):
; csel x0, x7, x10, eq
; ret
function %icmp_ult_i128(i128, i128) -> b1 {
function %icmp_ult_i128(i128, i128) -> i8 {
block0(v0: i128, v1: i128):
v2 = icmp ult v0, v1
return v2
@@ -65,7 +65,7 @@ block0(v0: i128, v1: i128):
; csel x0, x7, x10, eq
; ret
function %icmp_sle_i128(i128, i128) -> b1 {
function %icmp_sle_i128(i128, i128) -> i8 {
block0(v0: i128, v1: i128):
v2 = icmp sle v0, v1
return v2
@@ -79,7 +79,7 @@ block0(v0: i128, v1: i128):
; csel x0, x7, x10, eq
; ret
function %icmp_ule_i128(i128, i128) -> b1 {
function %icmp_ule_i128(i128, i128) -> i8 {
block0(v0: i128, v1: i128):
v2 = icmp ule v0, v1
return v2
@@ -93,7 +93,7 @@ block0(v0: i128, v1: i128):
; csel x0, x7, x10, eq
; ret
function %icmp_sgt_i128(i128, i128) -> b1 {
function %icmp_sgt_i128(i128, i128) -> i8 {
block0(v0: i128, v1: i128):
v2 = icmp sgt v0, v1
return v2
@@ -107,7 +107,7 @@ block0(v0: i128, v1: i128):
; csel x0, x7, x10, eq
; ret
function %icmp_ugt_i128(i128, i128) -> b1 {
function %icmp_ugt_i128(i128, i128) -> i8 {
block0(v0: i128, v1: i128):
v2 = icmp ugt v0, v1
return v2
@@ -121,7 +121,7 @@ block0(v0: i128, v1: i128):
; csel x0, x7, x10, eq
; ret
function %icmp_sge_i128(i128, i128) -> b1 {
function %icmp_sge_i128(i128, i128) -> i8 {
block0(v0: i128, v1: i128):
v2 = icmp sge v0, v1
return v2
@@ -135,7 +135,7 @@ block0(v0: i128, v1: i128):
; csel x0, x7, x10, eq
; ret
function %icmp_uge_i128(i128, i128) -> b1 {
function %icmp_uge_i128(i128, i128) -> i8 {
block0(v0: i128, v1: i128):
v2 = icmp uge v0, v1
return v2
@@ -471,3 +471,4 @@ block1:
; b label3
; block3:
; ret

16
cranelift/filetests/filetests/isa/aarch64/condops.clif
View File

@@ -737,7 +737,7 @@ block0(v0: i128, v1: i128, v2: i128):
; csdb
; ret
function %g(i8) -> b1 {
function %g(i8) -> i8 {
block0(v0: i8):
v3 = iconst.i8 42
v4 = ifcmp v0, v3
@@ -763,15 +763,14 @@ block0(v0: i8, v1: i8, v2: i8):
; orr w0, w5, w7
; ret
function %i(b1, i8, i8) -> i8 {
block0(v0: b1, v1: i8, v2: i8):
function %i(i8, i8, i8) -> i8 {
block0(v0: i8, v1: i8, v2: i8):
v3 = select.i8 v0, v1, v2
return v3
}
; block0:
; and w5, w0, #1
; subs wzr, w5, wzr
; ands wzr, w0, #255
; csel x0, x1, x2, ne
; ret
@@ -788,15 +787,14 @@ block0(v0: i32, v1: i8, v2: i8):
; csel x0, x1, x2, eq
; ret
function %i128_select(b1, i128, i128) -> i128 {
block0(v0: b1, v1: i128, v2: i128):
function %i128_select(i8, i128, i128) -> i128 {
block0(v0: i8, v1: i128, v2: i128):
v3 = select.i128 v0, v1, v2
return v3
}
; block0:
; and w8, w0, #1
; subs wzr, w8, wzr
; ands wzr, w0, #255
; csel x0, x2, x4, ne
; csel x1, x3, x5, ne
; ret

10
cranelift/filetests/filetests/isa/aarch64/constants.clif
View File

@@ -2,19 +2,19 @@ test compile precise-output
set unwind_info=false
target aarch64
function %f() -> b8 {
function %f() -> i8 {
block0:
v0 = bconst.b8 true
v0 = iconst.i8 -1
return v0
}
; block0:
; movz x0, #255
; movn x0, #0
; ret
function %f() -> b16 {
function %f() -> i16 {
block0:
v0 = bconst.b16 false
v0 = iconst.i16 0
return v0
}

112
cranelift/filetests/filetests/isa/aarch64/i128-bmask.clif Normal file
View File

@@ -0,0 +1,112 @@
test compile precise-output
target aarch64
function %bmask_i128_i128(i128) -> i128 {
block0(v0: i128):
v1 = bmask.i128 v0
return v1
}
; block0:
; orr x5, x0, x1
; subs xzr, x5, #0
; csetm x1, ne
; mov x0, x1
; ret
function %bmask_i128_i64(i128) -> i64 {
block0(v0: i128):
v1 = bmask.i64 v0
return v1
}
; block0:
; orr x4, x0, x1
; subs xzr, x4, #0
; csetm x0, ne
; ret
function %bmask_i128_i32(i128) -> i32 {
block0(v0: i128):
v1 = bmask.i32 v0
return v1
}
; block0:
; orr x4, x0, x1
; subs xzr, x4, #0
; csetm x0, ne
; ret
function %bmask_i128_i16(i128) -> i16 {
block0(v0: i128):
v1 = bmask.i16 v0
return v1
}
; block0:
; orr x4, x0, x1
; subs xzr, x4, #0
; csetm x0, ne
; ret
function %bmask_i128_i8(i128) -> i8 {
block0(v0: i128):
v1 = bmask.i8 v0
return v1
}
; block0:
; orr x4, x0, x1
; subs xzr, x4, #0
; csetm x0, ne
; ret
function %bmask_i64_i128(i64) -> i128 {
block0(v0: i64):
v1 = bmask.i128 v0
return v1
}
; block0:
; subs xzr, x0, #0
; csetm x1, ne
; mov x0, x1
; ret
function %bmask_i32_i128(i32) -> i128 {
block0(v0: i32):
v1 = bmask.i128 v0
return v1
}
; block0:
; subs xzr, x0, #0
; csetm x1, ne
; mov x0, x1
; ret
function %bmask_i16_i128(i16) -> i128 {
block0(v0: i16):
v1 = bmask.i128 v0
return v1
}
; block0:
; subs xzr, x0, #0
; csetm x1, ne
; mov x0, x1
; ret
function %bmask_i8_i128(i8) -> i128 {
block0(v0: i8):
v1 = bmask.i128 v0
return v1
}
; block0:
; subs xzr, x0, #0
; csetm x1, ne
; mov x0, x1
; ret

14
cranelift/filetests/filetests/isa/aarch64/iconst-icmp-small.clif
View File

@@ -10,16 +10,14 @@ function u0:0() -> i8 system_v {
block0:
v0 = iconst.i16 0xddcc
v1 = icmp.i16 ne v0, v0
v2 = bint.i8 v1
return v2
return v1
}
; block0:
; movz x2, #56780
; uxth w4, w2
; movz x6, #56780
; subs wzr, w4, w6, UXTH
; cset x9, ne
; and w0, w9, #1
; movz x1, #56780
; uxth w3, w1
; movz x5, #56780
; subs wzr, w3, w5, UXTH
; cset x0, ne
; ret

8
cranelift/filetests/filetests/isa/aarch64/reftypes.clif
View File

@@ -10,7 +10,7 @@ block0(v0: r64):
; block0:
; ret
function %f1(r64) -> b1 {
function %f1(r64) -> i8 {
block0(v0: r64):
v1 = is_null v0
return v1
@@ -21,7 +21,7 @@ block0(v0: r64):
; cset x0, eq
; ret
function %f2(r64) -> b1 {
function %f2(r64) -> i8 {
block0(v0: r64):
v1 = is_invalid v0
return v1
@@ -43,7 +43,7 @@ block0:
; ret
function %f4(r64, r64) -> r64, r64, r64 {
fn0 = %f(r64) -> b1
fn0 = %f(r64) -> i8
ss0 = explicit_slot 8
block0(v0: r64, v1: r64):
@@ -74,7 +74,7 @@ block3(v7: r64, v8: r64):
; mov x2, sp
; ldr x9, [sp, #8]
; str x9, [x2]
; and w3, w0, #1
; uxtb w3, w0
; cbz x3, label1 ; b label3
; block1:
; b label2

12
cranelift/filetests/filetests/isa/aarch64/simd-bitwise-compile.clif
View File

@@ -108,8 +108,8 @@ block0:
; bsl v0.16b, v0.16b, v4.16b, v5.16b
; ret
function %vselect_i16x8(b16x8, i16x8, i16x8) -> i16x8 {
block0(v0: b16x8, v1: i16x8, v2: i16x8):
function %vselect_i16x8(i16x8, i16x8, i16x8) -> i16x8 {
block0(v0: i16x8, v1: i16x8, v2: i16x8):
v3 = vselect v0, v1, v2
return v3
}
@@ -118,8 +118,8 @@ block0(v0: b16x8, v1: i16x8, v2: i16x8):
; bsl v0.16b, v0.16b, v1.16b, v2.16b
; ret
function %vselect_f32x4(b32x4, f32x4, f32x4) -> f32x4 {
block0(v0: b32x4, v1: f32x4, v2: f32x4):
function %vselect_f32x4(i32x4, f32x4, f32x4) -> f32x4 {
block0(v0: i32x4, v1: f32x4, v2: f32x4):
v3 = vselect v0, v1, v2
return v3
}
@@ -128,8 +128,8 @@ block0(v0: b32x4, v1: f32x4, v2: f32x4):
; bsl v0.16b, v0.16b, v1.16b, v2.16b
; ret
function %vselect_f64x2(b64x2, f64x2, f64x2) -> f64x2 {
block0(v0: b64x2, v1: f64x2, v2: f64x2):
function %vselect_f64x2(i64x2, f64x2, f64x2) -> f64x2 {
block0(v0: i64x2, v1: f64x2, v2: f64x2):
v3 = vselect v0, v1, v2
return v3
}

8
cranelift/filetests/filetests/isa/aarch64/simd-comparison-legalize.clif
View File

@@ -2,7 +2,7 @@ test compile precise-output
set enable_simd
target aarch64
function %icmp_ne_32x4(i32x4, i32x4) -> b32x4 {
function %icmp_ne_32x4(i32x4, i32x4) -> i32x4 {
block0(v0: i32x4, v1: i32x4):
v2 = icmp ne v0, v1
return v2
@@ -13,7 +13,7 @@ block0(v0: i32x4, v1: i32x4):
; mvn v0.16b, v4.16b
; ret
function %icmp_ugt_i32x4(i32x4, i32x4) -> b32x4 {
function %icmp_ugt_i32x4(i32x4, i32x4) -> i32x4 {
block0(v0: i32x4, v1: i32x4):
v2 = icmp ugt v0, v1
return v2
@@ -23,7 +23,7 @@ block0(v0: i32x4, v1: i32x4):
; cmhi v0.4s, v0.4s, v1.4s
; ret
function %icmp_sge_i16x8(i16x8, i16x8) -> b16x8 {
function %icmp_sge_i16x8(i16x8, i16x8) -> i16x8 {
block0(v0: i16x8, v1: i16x8):
v2 = icmp sge v0, v1
return v2
@@ -33,7 +33,7 @@ block0(v0: i16x8, v1: i16x8):
; cmge v0.8h, v0.8h, v1.8h
; ret
function %icmp_uge_i8x16(i8x16, i8x16) -> b8x16 {
function %icmp_uge_i8x16(i8x16, i8x16) -> i8x16 {
block0(v0: i8x16, v1: i8x16):
v2 = icmp uge v0, v1
return v2

6
cranelift/filetests/filetests/isa/aarch64/simd-lane-access-compile.clif
View File

@@ -59,10 +59,10 @@ block0(v0: i8):
; dup v0.16b, w0
; ret
function %splat_b16() -> b16x8 {
function %splat_i16() -> i16x8 {
block0:
v0 = bconst.b16 true
v1 = splat.b16x8 v0
v0 = iconst.i16 -1
v1 = splat.i16x8 v0
return v1
}

10
cranelift/filetests/filetests/isa/aarch64/simd-logical-compile.clif
View File

@@ -2,8 +2,8 @@ test compile precise-output
set enable_simd
target aarch64
function %bnot_b32x4(b32x4) -> b32x4 {
block0(v0: b32x4):
function %bnot_i32x4(i32x4) -> i32x4 {
block0(v0: i32x4):
v1 = bnot v0
return v1
}
@@ -12,8 +12,8 @@ block0(v0: b32x4):
; mvn v0.16b, v0.16b
; ret
function %vany_true_b32x4(b32x4) -> b1 {
block0(v0: b32x4):
function %vany_true_i32x4(i32x4) -> i8 {
block0(v0: i32x4):
v1 = vany_true v0
return v1
}
@@ -25,7 +25,7 @@ block0(v0: b32x4):
; cset x0, ne
; ret
function %vall_true_i64x2(i64x2) -> b1 {
function %vall_true_i64x2(i64x2) -> i8 {
block0(v0: i64x2):
v1 = vall_true v0
return v1

29
cranelift/filetests/filetests/isa/aarch64/simd-valltrue.clif
View File

@@ -2,8 +2,8 @@ test compile precise-output
set unwind_info=false
target aarch64
function %fn0(b8x8) -> b1 {
block0(v0: b8x8):
function %fn0(i8x8) -> i8 {
block0(v0: i8x8):
v1 = vall_true v0
return v1
}
@@ -15,8 +15,8 @@ block0(v0: b8x8):
; cset x0, ne
; ret
function %fn1(b8x16) -> b1 {
block0(v0: b8x16):
function %fn1(i8x16) -> i8 {
block0(v0: i8x16):
v1 = vall_true v0
return v1
}
@@ -28,8 +28,8 @@ block0(v0: b8x16):
; cset x0, ne
; ret
function %fn2(b16x4) -> b1 {
block0(v0: b16x4):
function %fn2(i16x4) -> i8 {
block0(v0: i16x4):
v1 = vall_true v0
return v1
}
@@ -41,8 +41,8 @@ block0(v0: b16x4):
; cset x0, ne
; ret
function %fn3(b16x8) -> b1 {
block0(v0: b16x8):
function %fn3(i16x8) -> i8 {
block0(v0: i16x8):
v1 = vall_true v0
return v1
}
@@ -54,8 +54,8 @@ block0(v0: b16x8):
; cset x0, ne
; ret
function %fn4(b32x2) -> b1 {
block0(v0: b32x2):
function %fn4(i32x2) -> i8 {
block0(v0: i32x2):
v1 = vall_true v0
return v1
}
@@ -67,8 +67,8 @@ block0(v0: b32x2):
; cset x0, ne
; ret
function %fn5(b32x4) -> b1 {
block0(v0: b32x4):
function %fn5(i32x4) -> i8 {
block0(v0: i32x4):
v1 = vall_true v0
return v1
}
@@ -80,8 +80,8 @@ block0(v0: b32x4):
; cset x0, ne
; ret
function %fn6(b64x2) -> b1 {
block0(v0: b64x2):
function %fn6(i64x2) -> i8 {
block0(v0: i64x2):
v1 = vall_true v0
return v1
}
@@ -92,3 +92,4 @@ block0(v0: b64x2):
; fcmp d5, d5
; cset x0, eq
; ret

12
cranelift/filetests/filetests/isa/aarch64/simd.clif
View File

@@ -28,18 +28,6 @@ block0:
; dup v0.8h, w2
; ret
function %f3() -> b8x16 {
block0:
v0 = bconst.b32 true
v1 = breduce.b8 v0
v2 = splat.b8x16 v1
return v2
}
; block0:
; movi v0.16b, #255
; ret
function %f4(i32, i8x16, i8x16) -> i8x16 {
block0(v0: i32, v1: i8x16, v2: i8x16):
v3 = select v0, v1, v2

4
cranelift/filetests/filetests/isa/aarch64/stack.clif
View File

@@ -123,10 +123,10 @@ block0(v0: i64):
; ldp fp, lr, [sp], #16
; ret
function %b1_spill_slot(b1) -> b1, i64 {
function %i8_spill_slot(i8) -> i8, i64 {
ss0 = explicit_slot 1000
block0(v0: b1):
block0(v0: i8):
v1 = iconst.i64 1
v2 = iconst.i64 2
v3 = iconst.i64 3