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cranelift: Remove booleans (#5031)

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Remove the boolean types from cranelift, and the associated instructions breduce, bextend, bconst, and bint. Standardize on using 1/0 for the return value from instructions that produce scalar boolean results, and -1/0 for boolean vector elements.

Fixes #3205

Co-authored-by: Afonso Bordado <afonso360@users.noreply.github.com>
Co-authored-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
Co-authored-by: Chris Fallin <chris@cfallin.org>
This commit is contained in:
Trevor Elliott
2022-10-17 16:00:27 -07:00
committed by GitHub
parent 766ecb561e
commit 32a7593c94
242 changed files with 7695 additions and 10010 deletions
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6
cranelift/codegen/src/isa/riscv64/inst/args.rs
View File

@@ -1189,10 +1189,8 @@ impl LoadOP {
return if t == F32 { Self::Flw } else { Self::Fld };
}
match t {
B1 | B8 => Self::Lbu,
B16 => Self::Lhu,
B32 | R32 => Self::Lwu,
B64 | R64 | I64 => Self::Ld,
R32 => Self::Lwu,
R64 | I64 => Self::Ld,
I8 => Self::Lb,
I16 => Self::Lh,

7
cranelift/codegen/src/isa/riscv64/inst/emit.rs
View File

@@ -1039,9 +1039,8 @@ impl MachInstEmit for Inst {
&Inst::CondBr {
taken,
not_taken,
kind,
mut kind,
} => {
let mut kind = kind;
kind.rs1 = allocs.next(kind.rs1);
kind.rs2 = allocs.next(kind.rs2);
match taken {
@@ -1385,13 +1384,13 @@ impl MachInstEmit for Inst {
.for_each(|i| i.emit(&[], sink, emit_info, state));
sink.bind_label(label_true);
Inst::load_imm12(rd, Imm12::from_bits(-1)).emit(&[], sink, emit_info, state);
Inst::load_imm12(rd, Imm12::TRUE).emit(&[], sink, emit_info, state);
Inst::Jal {
dest: BranchTarget::offset(Inst::INSTRUCTION_SIZE * 2),
}
.emit(&[], sink, emit_info, state);
sink.bind_label(label_false);
Inst::load_imm12(rd, Imm12::from_bits(0)).emit(&[], sink, emit_info, state);
Inst::load_imm12(rd, Imm12::FALSE).emit(&[], sink, emit_info, state);
}
&Inst::AtomicCas {
offset,

31
cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs
View File

@@ -572,16 +572,6 @@ fn test_riscv64_binemit() {
"lb a0,100(a1)",
0x6458503,
));
insns.push(TestUnit::new(
Inst::Load {
rd: writable_a0(),
op: LoadOP::Lbu,
flags: MemFlags::new(),
from: AMode::RegOffset(a1(), 100, B8),
},
"lbu a0,100(a1)",
0x645c503,
));
insns.push(TestUnit::new(
Inst::Load {
rd: writable_a0(),
@@ -593,17 +583,6 @@ fn test_riscv64_binemit() {
0x6459503,
));
insns.push(TestUnit::new(
Inst::Load {
rd: writable_a0(),
op: LoadOP::Lhu,
flags: MemFlags::new(),
from: AMode::RegOffset(a1(), 100, B16),
},
"lhu a0,100(a1)",
0x645d503,
));
insns.push(TestUnit::new(
Inst::Load {
rd: writable_a0(),
@@ -615,16 +594,6 @@ fn test_riscv64_binemit() {
0x645a503,
));
insns.push(TestUnit::new(
Inst::Load {
rd: writable_a0(),
op: LoadOP::Lwu,
flags: MemFlags::new(),
from: AMode::RegOffset(a1(), 100, B32),
},
"lwu a0,100(a1)",
0x645e503,
));
insns.push(TestUnit::new(
Inst::Load {
rd: writable_a0(),

2
cranelift/codegen/src/isa/riscv64/inst/imms.rs
View File

@@ -12,7 +12,7 @@ pub struct Imm12 {
impl Imm12 {
pub(crate) const FALSE: Self = Self { bits: 0 };
pub(crate) const TRUE: Self = Self { bits: -1 };
pub(crate) const TRUE: Self = Self { bits: 1 };
pub fn maybe_from_u64(val: u64) -> Option<Imm12> {
let sign_bit = 1 << 11;
if val == 0 {

19
cranelift/codegen/src/isa/riscv64/inst/mod.rs
View File

@@ -6,9 +6,7 @@
use crate::binemit::{Addend, CodeOffset, Reloc};
pub use crate::ir::condcodes::IntCC;
use crate::ir::types::{
B1, B128, B16, B32, B64, B8, F32, F64, FFLAGS, I128, I16, I32, I64, I8, IFLAGS, R32, R64,
};
use crate::ir::types::{F32, F64, FFLAGS, I128, I16, I32, I64, I8, IFLAGS, R32, R64};
pub use crate::ir::{ExternalName, MemFlags, Opcode, SourceLoc, Type, ValueLabel};
use crate::isa::CallConv;
@@ -691,14 +689,11 @@ impl MachInst for Inst {
fn gen_constant<F: FnMut(Type) -> Writable<Reg>>(
to_regs: ValueRegs<Writable<Reg>>,
mut value: u128,
value: u128,
ty: Type,
mut alloc_tmp: F,
) -> SmallVec<[Inst; 4]> {
if ty.is_bool() && value != 0 {
value = !0;
}
if (ty.bits() <= 64 && (ty.is_bool() || ty.is_int())) || ty == R32 || ty == R64 {
if (ty.bits() <= 64 && ty.is_int()) || ty == R32 || ty == R64 {
return Inst::load_constant_u64(to_regs.only_reg().unwrap(), value as u64);
};
match ty {
@@ -708,7 +703,7 @@ impl MachInst for Inst {
F64 => {
Inst::load_fp_constant64(to_regs.only_reg().unwrap(), value as u64, alloc_tmp(I64))
}
I128 | B128 => {
I128 => {
let mut insts = SmallInstVec::new();
insts.extend(Inst::load_constant_u64(
to_regs.regs()[0],
@@ -736,17 +731,11 @@ impl MachInst for Inst {
I16 => Ok((&[RegClass::Int], &[I16])),
I32 => Ok((&[RegClass::Int], &[I32])),
I64 => Ok((&[RegClass::Int], &[I64])),
B1 => Ok((&[RegClass::Int], &[B1])),
B8 => Ok((&[RegClass::Int], &[B8])),
B16 => Ok((&[RegClass::Int], &[B16])),
B32 => Ok((&[RegClass::Int], &[B32])),
B64 => Ok((&[RegClass::Int], &[B64])),
R32 => panic!("32-bit reftype pointer should never be seen on riscv64"),
R64 => Ok((&[RegClass::Int], &[R64])),
F32 => Ok((&[RegClass::Float], &[F32])),
F64 => Ok((&[RegClass::Float], &[F64])),
I128 => Ok((&[RegClass::Int, RegClass::Int], &[I64, I64])),
B128 => Ok((&[RegClass::Int, RegClass::Int], &[B64, B64])),
IFLAGS => Ok((&[RegClass::Int], &[IFLAGS])),
FFLAGS => Ok((&[RegClass::Int], &[FFLAGS])),
_ => Err(CodegenError::Unsupported(format!(

2
cranelift/codegen/src/isa/riscv64/inst/unwind/systemv.rs
View File

@@ -143,7 +143,7 @@ mod tests {
assert_eq!(
format!("{:?}", fde),
"FrameDescriptionEntry { address: Constant(4321), length: 12, lsda: None, instructions: [] }"
"FrameDescriptionEntry { address: Constant(4321), length: 16, lsda: None, instructions: [] }"
);
}