From 30d206779ec370eac8c0e2e527f44ced4aa0f912 Mon Sep 17 00:00:00 2001 From: Nick Fitzgerald Date: Fri, 5 Nov 2021 14:28:03 -0700 Subject: [PATCH] x64: Remove some unreachable code that's been ported to ISLE --- cranelift/codegen/src/isa/x64/lower.rs | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs index 65e94e396a..312d3423aa 100644 --- a/cranelift/codegen/src/isa/x64/lower.rs +++ b/cranelift/codegen/src/isa/x64/lower.rs @@ -1545,20 +1545,7 @@ fn lower_insn_to_regs>( } else if ty == types::I64X2 { unreachable!("implemented in ISLE: {}", ctx.dfg().display_inst(insn)); } else if ty.lane_count() > 1 { - // Emit single instruction lowerings for the remaining vector - // multiplications. - let sse_op = match ty { - types::I16X8 => SseOpcode::Pmullw, - types::I32X4 => SseOpcode::Pmulld, - _ => panic!("Unsupported type for packed imul instruction: {}", ty), - }; - let lhs = put_input_in_reg(ctx, inputs[0]); - let rhs = input_to_reg_mem(ctx, inputs[1]); - let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap(); - - // Move the `lhs` to the same register as `dst`. - ctx.emit(Inst::gen_move(dst, lhs, ty)); - ctx.emit(Inst::xmm_rm_r(sse_op, rhs, dst)); + unreachable!("implemented in ISLE: {}", ctx.dfg().display_inst(insn)); } else if ty == types::I128 || ty == types::B128 { // Handle 128-bit multiplications. let lhs = put_input_in_regs(ctx, inputs[0]);