diff --git a/lib/cretonne/meta/gen_registers.py b/lib/cretonne/meta/gen_registers.py
index c535f44c22..e36434f4d6 100644
--- a/lib/cretonne/meta/gen_registers.py
+++ b/lib/cretonne/meta/gen_registers.py
@@ -33,8 +33,8 @@ def gen_regclass(rc, fmt):
     """
     Emit a static data definition for a register class.
     """
-    fmt.comment(rc.name)
     with fmt.indented('RegClassData {', '},'):
+        fmt.line('name: "{}",'.format(rc.name))
         fmt.line('index: {},'.format(rc.index))
         fmt.line('width: {},'.format(rc.width))
         fmt.line('subclasses: 0x{:x},'.format(rc.subclass_mask()))
diff --git a/lib/cretonne/src/isa/registers.rs b/lib/cretonne/src/isa/registers.rs
index 588fc0b14d..c785ab2ac9 100644
--- a/lib/cretonne/src/isa/registers.rs
+++ b/lib/cretonne/src/isa/registers.rs
@@ -99,6 +99,9 @@ pub type RegClass = &'static RegClassData;
 /// A register class can be a subset of another register class. The top-level register classes are
 /// disjoint.
 pub struct RegClassData {
+    /// The name of the register class.
+    pub name: &'static str,
+
     /// The index of this class in the ISA's RegInfo description.
     pub index: u8,
 
diff --git a/lib/cretonne/src/regalloc/allocatable_set.rs b/lib/cretonne/src/regalloc/allocatable_set.rs
index 2c608b0a16..39058c04e4 100644
--- a/lib/cretonne/src/regalloc/allocatable_set.rs
+++ b/lib/cretonne/src/regalloc/allocatable_set.rs
@@ -118,12 +118,14 @@ mod tests {
 
     // Register classes for testing.
     const GPR: RegClass = &RegClassData {
+        name: "GPR",
         index: 0,
         width: 1,
         subclasses: 0,
         mask: [0xf0000000, 0x0000000f, 0],
     };
     const DPR: RegClass = &RegClassData {
+        name: "DPR",
         index: 0,
         width: 2,
         subclasses: 0,