Add an enable_e setting for the RV32E instruction set.

This limited RISC-V version only has registers %x0 - %x15.

Make sure the ABI lowering code doesn't use the banned registers for
arguments.

lib/cretonne/src/isa/riscv/mod.rs

@@ -79,8 +79,7 @@ impl TargetIsa for Isa {
     }
 
     fn legalize_signature(&self, sig: &mut Signature, current: bool) {
-        // We can pass in `self.isa_flags` too, if we need it.
-        abi::legalize_signature(sig, &self.shared_flags, current)
+        abi::legalize_signature(sig, &self.shared_flags, &self.isa_flags, current)
     }
 
     fn regclass_for_abi_type(&self, ty: Type) -> RegClass {