Update rustfmt to 0.9.0.

lib/cretonne/src/isa/riscv/abi.rs

@@ -86,10 +86,12 @@ impl ArgAssigner for Args {
 }
 
 /// Legalize `sig` for RISC-V.
-pub fn legalize_signature(sig: &mut ir::Signature,
-                          flags: &shared_settings::Flags,
-                          isa_flags: &settings::Flags,
-                          current: bool) {
+pub fn legalize_signature(
+    sig: &mut ir::Signature,
+    flags: &shared_settings::Flags,
+    isa_flags: &settings::Flags,
+    current: bool,
+) {
     let bits = if flags.is_64bit() { 64 } else { 32 };
 
     let mut args = Args::new(bits, isa_flags.enable_e());

lib/cretonne/src/isa/riscv/binemit.rs

@@ -29,11 +29,7 @@ impl Into<Reloc> for RelocKind {
 ///       25  20  15     12  7      0
 ///
 /// Encoding bits: `opcode[6:2] | (funct3 << 5) | (funct7 << 8)`.
-fn put_r<CS: CodeSink + ?Sized>(bits: u16,
-                                rs1: RegUnit,
-                                rs2: RegUnit,
-                                rd: RegUnit,
-                                sink: &mut CS) {
+fn put_r<CS: CodeSink + ?Sized>(bits: u16, rs1: RegUnit, rs2: RegUnit, rd: RegUnit, sink: &mut CS) {
     let bits = bits as u32;
     let opcode5 = bits & 0x1f;
     let funct3 = (bits >> 5) & 0x7;
@@ -63,11 +59,13 @@ fn put_r<CS: CodeSink + ?Sized>(bits: u16,
 /// Both funct7 and shamt contribute to bit 25. In RV64, shamt uses it for shifts > 31.
 ///
 /// Encoding bits: `opcode[6:2] | (funct3 << 5) | (funct7 << 8)`.
-fn put_rshamt<CS: CodeSink + ?Sized>(bits: u16,
-                                     rs1: RegUnit,
-                                     shamt: i64,
-                                     rd: RegUnit,
-                                     sink: &mut CS) {
+fn put_rshamt<CS: CodeSink + ?Sized>(
+    bits: u16,
+    rs1: RegUnit,
+    shamt: i64,
+    rd: RegUnit,
+    sink: &mut CS,
+) {
     let bits = bits as u32;
     let opcode5 = bits & 0x1f;
     let funct3 = (bits >> 5) & 0x7;

lib/cretonne/src/isa/riscv/mod.rs

@@ -29,19 +29,20 @@ pub fn isa_builder() -> IsaBuilder {
     }
 }
 
-fn isa_constructor(shared_flags: shared_settings::Flags,
-                   builder: &shared_settings::Builder)
-                   -> Box<TargetIsa> {
+fn isa_constructor(
+    shared_flags: shared_settings::Flags,
+    builder: &shared_settings::Builder,
+) -> Box<TargetIsa> {
     let level1 = if shared_flags.is_64bit() {
         &enc_tables::LEVEL1_RV64[..]
     } else {
         &enc_tables::LEVEL1_RV32[..]
     };
     Box::new(Isa {
-                 isa_flags: settings::Flags::new(&shared_flags, builder),
-                 shared_flags,
-                 cpumode: level1,
-             })
+        isa_flags: settings::Flags::new(&shared_flags, builder),
+        shared_flags,
+        cpumode: level1,
+    })
 }
 
 impl TargetIsa for Isa {
@@ -61,21 +62,24 @@ impl TargetIsa for Isa {
         enc_tables::INFO.clone()
     }
 
-    fn legal_encodings<'a>(&'a self,
-                           dfg: &'a ir::DataFlowGraph,
-                           inst: &'a ir::InstructionData,
-                           ctrl_typevar: ir::Type)
-                           -> Encodings<'a> {
-        lookup_enclist(ctrl_typevar,
-                       inst,
-                       dfg,
-                       self.cpumode,
-                       &enc_tables::LEVEL2[..],
-                       &enc_tables::ENCLISTS[..],
-                       &enc_tables::LEGALIZE_ACTIONS[..],
-                       &enc_tables::RECIPE_PREDICATES[..],
-                       &enc_tables::INST_PREDICATES[..],
-                       self.isa_flags.predicate_view())
+    fn legal_encodings<'a>(
+        &'a self,
+        dfg: &'a ir::DataFlowGraph,
+        inst: &'a ir::InstructionData,
+        ctrl_typevar: ir::Type,
+    ) -> Encodings<'a> {
+        lookup_enclist(
+            ctrl_typevar,
+            inst,
+            dfg,
+            self.cpumode,
+            &enc_tables::LEVEL2[..],
+            &enc_tables::ENCLISTS[..],
+            &enc_tables::LEGALIZE_ACTIONS[..],
+            &enc_tables::RECIPE_PREDICATES[..],
+            &enc_tables::INST_PREDICATES[..],
+            self.isa_flags.predicate_view(),
+        )
     }
 
     fn legalize_signature(&self, sig: &mut ir::Signature, current: bool) {
@@ -90,11 +94,13 @@ impl TargetIsa for Isa {
         abi::allocatable_registers(func, &self.isa_flags)
     }
 
-    fn emit_inst(&self,
-                 func: &ir::Function,
-                 inst: ir::Inst,
-                 divert: &mut regalloc::RegDiversions,
-                 sink: &mut CodeSink) {
+    fn emit_inst(
+        &self,
+        func: &ir::Function,
+        inst: ir::Inst,
+        divert: &mut regalloc::RegDiversions,
+        sink: &mut CodeSink,
+    ) {
         binemit::emit_inst(func, inst, divert, sink)
     }
 

lib/cretonne/src/isa/riscv/settings.rs

@@ -18,14 +18,16 @@ mod tests {
         let shared = settings::Flags::new(&settings::builder());
         let b = builder();
         let f = Flags::new(&shared, &b);
-        assert_eq!(f.to_string(),
-                   "[riscv]\n\
+        assert_eq!(
+            f.to_string(),
+            "[riscv]\n\
                     supports_m = false\n\
                     supports_a = false\n\
                     supports_f = false\n\
                     supports_d = false\n\
                     enable_m = true\n\
-                    enable_e = false\n");
+                    enable_e = false\n"
+        );
         // Predicates are not part of the Display output.
         assert_eq!(f.full_float(), false);
     }