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Update rustfmt to 0.9.0.

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This commit is contained in:
Dan Gohman
2017-08-31 10:44:59 -07:00
parent 46fb64cbb4
commit 2efdc0ed37
111 changed files with 4692 additions and 3379 deletions
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8
lib/cretonne/src/isa/arm32/abi.rs
View File

@@ -7,9 +7,11 @@ use settings as shared_settings;
use super::registers::{S, D, Q, GPR};
/// Legalize `sig`.
pub fn legalize_signature(_sig: &mut ir::Signature,
_flags: &shared_settings::Flags,
_current: bool) {
pub fn legalize_signature(
_sig: &mut ir::Signature,
_flags: &shared_settings::Flags,
_current: bool,
) {
unimplemented!()
}

60
lib/cretonne/src/isa/arm32/mod.rs
View File

@@ -29,19 +29,20 @@ pub fn isa_builder() -> IsaBuilder {
}
}
fn isa_constructor(shared_flags: shared_settings::Flags,
builder: &shared_settings::Builder)
-> Box<TargetIsa> {
fn isa_constructor(
shared_flags: shared_settings::Flags,
builder: &shared_settings::Builder,
) -> Box<TargetIsa> {
let level1 = if shared_flags.is_compressed() {
&enc_tables::LEVEL1_T32[..]
} else {
&enc_tables::LEVEL1_A32[..]
};
Box::new(Isa {
isa_flags: settings::Flags::new(&shared_flags, builder),
shared_flags,
cpumode: level1,
})
isa_flags: settings::Flags::new(&shared_flags, builder),
shared_flags,
cpumode: level1,
})
}
impl TargetIsa for Isa {
@@ -61,21 +62,24 @@ impl TargetIsa for Isa {
enc_tables::INFO.clone()
}
fn legal_encodings<'a>(&'a self,
dfg: &'a ir::DataFlowGraph,
inst: &'a ir::InstructionData,
ctrl_typevar: ir::Type)
-> Encodings<'a> {
lookup_enclist(ctrl_typevar,
inst,
dfg,
self.cpumode,
&enc_tables::LEVEL2[..],
&enc_tables::ENCLISTS[..],
&enc_tables::LEGALIZE_ACTIONS[..],
&enc_tables::RECIPE_PREDICATES[..],
&enc_tables::INST_PREDICATES[..],
self.isa_flags.predicate_view())
fn legal_encodings<'a>(
&'a self,
dfg: &'a ir::DataFlowGraph,
inst: &'a ir::InstructionData,
ctrl_typevar: ir::Type,
) -> Encodings<'a> {
lookup_enclist(
ctrl_typevar,
inst,
dfg,
self.cpumode,
&enc_tables::LEVEL2[..],
&enc_tables::ENCLISTS[..],
&enc_tables::LEGALIZE_ACTIONS[..],
&enc_tables::RECIPE_PREDICATES[..],
&enc_tables::INST_PREDICATES[..],
self.isa_flags.predicate_view(),
)
}
fn legalize_signature(&self, sig: &mut ir::Signature, current: bool) {
@@ -90,11 +94,13 @@ impl TargetIsa for Isa {
abi::allocatable_registers(func)
}
fn emit_inst(&self,
func: &ir::Function,
inst: ir::Inst,
divert: &mut regalloc::RegDiversions,
sink: &mut CodeSink) {
fn emit_inst(
&self,
func: &ir::Function,
inst: ir::Inst,
divert: &mut regalloc::RegDiversions,
sink: &mut CodeSink,
) {
binemit::emit_inst(func, inst, divert, sink)
}

8
lib/cretonne/src/isa/arm64/abi.rs
View File

@@ -7,9 +7,11 @@ use settings as shared_settings;
use super::registers::{GPR, FPR};
/// Legalize `sig`.
pub fn legalize_signature(_sig: &mut ir::Signature,
_flags: &shared_settings::Flags,
_current: bool) {
pub fn legalize_signature(
_sig: &mut ir::Signature,
_flags: &shared_settings::Flags,
_current: bool,
) {
unimplemented!()
}

58
lib/cretonne/src/isa/arm64/mod.rs
View File

@@ -28,13 +28,14 @@ pub fn isa_builder() -> IsaBuilder {
}
}
fn isa_constructor(shared_flags: shared_settings::Flags,
builder: &shared_settings::Builder)
-> Box<TargetIsa> {
fn isa_constructor(
shared_flags: shared_settings::Flags,
builder: &shared_settings::Builder,
) -> Box<TargetIsa> {
Box::new(Isa {
isa_flags: settings::Flags::new(&shared_flags, builder),
shared_flags,
})
isa_flags: settings::Flags::new(&shared_flags, builder),
shared_flags,
})
}
impl TargetIsa for Isa {
@@ -54,21 +55,24 @@ impl TargetIsa for Isa {
enc_tables::INFO.clone()
}
fn legal_encodings<'a>(&'a self,
dfg: &'a ir::DataFlowGraph,
inst: &'a ir::InstructionData,
ctrl_typevar: ir::Type)
-> Encodings<'a> {
lookup_enclist(ctrl_typevar,
inst,
dfg,
&enc_tables::LEVEL1_A64[..],
&enc_tables::LEVEL2[..],
&enc_tables::ENCLISTS[..],
&enc_tables::LEGALIZE_ACTIONS[..],
&enc_tables::RECIPE_PREDICATES[..],
&enc_tables::INST_PREDICATES[..],
self.isa_flags.predicate_view())
fn legal_encodings<'a>(
&'a self,
dfg: &'a ir::DataFlowGraph,
inst: &'a ir::InstructionData,
ctrl_typevar: ir::Type,
) -> Encodings<'a> {
lookup_enclist(
ctrl_typevar,
inst,
dfg,
&enc_tables::LEVEL1_A64[..],
&enc_tables::LEVEL2[..],
&enc_tables::ENCLISTS[..],
&enc_tables::LEGALIZE_ACTIONS[..],
&enc_tables::RECIPE_PREDICATES[..],
&enc_tables::INST_PREDICATES[..],
self.isa_flags.predicate_view(),
)
}
fn legalize_signature(&self, sig: &mut ir::Signature, current: bool) {
@@ -83,11 +87,13 @@ impl TargetIsa for Isa {
abi::allocatable_registers(func)
}
fn emit_inst(&self,
func: &ir::Function,
inst: ir::Inst,
divert: &mut regalloc::RegDiversions,
sink: &mut CodeSink) {
fn emit_inst(
&self,
func: &ir::Function,
inst: ir::Inst,
divert: &mut regalloc::RegDiversions,
sink: &mut CodeSink,
) {
binemit::emit_inst(func, inst, divert, sink)
}

69
lib/cretonne/src/isa/enc_tables.rs
View File

@@ -103,19 +103,21 @@ impl<OffT: Into<u32> + Copy> Table<Opcode> for [Level2Entry<OffT>] {
/// list.
///
/// Returns an iterator that produces legal encodings for `inst`.
pub fn lookup_enclist<'a, OffT1, OffT2>(ctrl_typevar: Type,
inst: &'a InstructionData,
dfg: &'a DataFlowGraph,
level1_table: &'static [Level1Entry<OffT1>],
level2_table: &'static [Level2Entry<OffT2>],
enclist: &'static [EncListEntry],
legalize_actions: &'static [Legalize],
recipe_preds: &'static [RecipePredicate],
inst_preds: &'static [InstPredicate],
isa_preds: PredicateView<'a>)
-> Encodings<'a>
where OffT1: Into<u32> + Copy,
OffT2: Into<u32> + Copy
pub fn lookup_enclist<'a, OffT1, OffT2>(
ctrl_typevar: Type,
inst: &'a InstructionData,
dfg: &'a DataFlowGraph,
level1_table: &'static [Level1Entry<OffT1>],
level2_table: &'static [Level2Entry<OffT2>],
enclist: &'static [EncListEntry],
legalize_actions: &'static [Legalize],
recipe_preds: &'static [RecipePredicate],
inst_preds: &'static [InstPredicate],
isa_preds: PredicateView<'a>,
) -> Encodings<'a>
where
OffT1: Into<u32> + Copy,
OffT2: Into<u32> + Copy,
{
let (offset, legalize) = match probe(level1_table, ctrl_typevar, ctrl_typevar.index()) {
Err(l1idx) => {
@@ -144,15 +146,17 @@ pub fn lookup_enclist<'a, OffT1, OffT2>(ctrl_typevar: Type,
// Now we have an offset into `enclist` that is `!0` when no encoding list could be found.
// The default legalization code is always valid.
Encodings::new(offset,
legalize,
inst,
dfg,
enclist,
legalize_actions,
recipe_preds,
inst_preds,
isa_preds)
Encodings::new(
offset,
legalize,
inst,
dfg,
enclist,
legalize_actions,
recipe_preds,
inst_preds,
isa_preds,
)
}
/// Encoding list entry.
@@ -187,16 +191,17 @@ impl<'a> Encodings<'a> {
/// This iterator provides search for encodings that applies to the given instruction. The
/// encoding lists are laid out such that first call to `next` returns valid entry in the list
/// or `None`.
pub fn new(offset: usize,
legalize: LegalizeCode,
inst: &'a InstructionData,
dfg: &'a DataFlowGraph,
enclist: &'static [EncListEntry],
legalize_actions: &'static [Legalize],
recipe_preds: &'static [RecipePredicate],
inst_preds: &'static [InstPredicate],
isa_preds: PredicateView<'a>)
-> Self {
pub fn new(
offset: usize,
legalize: LegalizeCode,
inst: &'a InstructionData,
dfg: &'a DataFlowGraph,
enclist: &'static [EncListEntry],
legalize_actions: &'static [Legalize],
recipe_preds: &'static [RecipePredicate],
inst_preds: &'static [InstPredicate],
isa_preds: PredicateView<'a>,
) -> Self {
Encodings {
offset,
inst,

10
lib/cretonne/src/isa/encoding.rs
View File

@@ -66,10 +66,12 @@ pub struct DisplayEncoding {
impl fmt::Display for DisplayEncoding {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
if self.encoding.is_legal() {
write!(f,
"{}#{:02x}",
self.recipe_names[self.encoding.recipe()],
self.encoding.bits)
write!(
f,
"{}#{:02x}",
self.recipe_names[self.encoding.recipe()],
self.encoding.bits
)
} else {
write!(f, "-")
}

11
lib/cretonne/src/isa/intel/abi.rs
View File

@@ -87,9 +87,7 @@ impl ArgAssigner for Args {
}
/// Legalize `sig`.
pub fn legalize_signature(sig: &mut ir::Signature,
flags: &shared_settings::Flags,
_current: bool) {
pub fn legalize_signature(sig: &mut ir::Signature, flags: &shared_settings::Flags, _current: bool) {
let bits = if flags.is_64bit() { 64 } else { 32 };
let mut args = Args::new(bits, &ARG_GPRS, 8);
@@ -105,9 +103,10 @@ pub fn regclass_for_abi_type(ty: ir::Type) -> RegClass {
}
/// Get the set of allocatable registers for `func`.
pub fn allocatable_registers(_func: &ir::Function,
flags: &shared_settings::Flags)
-> AllocatableSet {
pub fn allocatable_registers(
_func: &ir::Function,
flags: &shared_settings::Flags,
) -> AllocatableSet {
let mut regs = AllocatableSet::new();
regs.take(GPR, RU::rsp as RegUnit);
regs.take(GPR, RU::rbp as RegUnit);

60
lib/cretonne/src/isa/intel/mod.rs
View File

@@ -29,19 +29,20 @@ pub fn isa_builder() -> IsaBuilder {
}
}
fn isa_constructor(shared_flags: shared_settings::Flags,
builder: &shared_settings::Builder)
-> Box<TargetIsa> {
fn isa_constructor(
shared_flags: shared_settings::Flags,
builder: &shared_settings::Builder,
) -> Box<TargetIsa> {
let level1 = if shared_flags.is_64bit() {
&enc_tables::LEVEL1_I64[..]
} else {
&enc_tables::LEVEL1_I32[..]
};
Box::new(Isa {
isa_flags: settings::Flags::new(&shared_flags, builder),
shared_flags,
cpumode: level1,
})
isa_flags: settings::Flags::new(&shared_flags, builder),
shared_flags,
cpumode: level1,
})
}
impl TargetIsa for Isa {
@@ -61,21 +62,24 @@ impl TargetIsa for Isa {
enc_tables::INFO.clone()
}
fn legal_encodings<'a>(&'a self,
dfg: &'a ir::DataFlowGraph,
inst: &'a ir::InstructionData,
ctrl_typevar: ir::Type)
-> Encodings<'a> {
lookup_enclist(ctrl_typevar,
inst,
dfg,
self.cpumode,
&enc_tables::LEVEL2[..],
&enc_tables::ENCLISTS[..],
&enc_tables::LEGALIZE_ACTIONS[..],
&enc_tables::RECIPE_PREDICATES[..],
&enc_tables::INST_PREDICATES[..],
self.isa_flags.predicate_view())
fn legal_encodings<'a>(
&'a self,
dfg: &'a ir::DataFlowGraph,
inst: &'a ir::InstructionData,
ctrl_typevar: ir::Type,
) -> Encodings<'a> {
lookup_enclist(
ctrl_typevar,
inst,
dfg,
self.cpumode,
&enc_tables::LEVEL2[..],
&enc_tables::ENCLISTS[..],
&enc_tables::LEGALIZE_ACTIONS[..],
&enc_tables::RECIPE_PREDICATES[..],
&enc_tables::INST_PREDICATES[..],
self.isa_flags.predicate_view(),
)
}
fn legalize_signature(&self, sig: &mut ir::Signature, current: bool) {
@@ -90,11 +94,13 @@ impl TargetIsa for Isa {
abi::allocatable_registers(func, &self.shared_flags)
}
fn emit_inst(&self,
func: &ir::Function,
inst: ir::Inst,
divert: &mut regalloc::RegDiversions,
sink: &mut CodeSink) {
fn emit_inst(
&self,
func: &ir::Function,
inst: ir::Inst,
divert: &mut regalloc::RegDiversions,
sink: &mut CodeSink,
) {
binemit::emit_inst(func, inst, divert, sink)
}

34
lib/cretonne/src/isa/mod.rs
View File

@@ -155,11 +155,12 @@ pub trait TargetIsa {
fn register_info(&self) -> RegInfo;
/// Returns an iterartor over legal encodings for the instruction.
fn legal_encodings<'a>(&'a self,
dfg: &'a ir::DataFlowGraph,
inst: &'a ir::InstructionData,
ctrl_typevar: ir::Type)
-> Encodings<'a>;
fn legal_encodings<'a>(
&'a self,
dfg: &'a ir::DataFlowGraph,
inst: &'a ir::InstructionData,
ctrl_typevar: ir::Type,
) -> Encodings<'a>;
/// Encode an instruction after determining it is legal.
///
@@ -167,11 +168,12 @@ pub trait TargetIsa {
/// Otherwise, return `Legalize` action.
///
/// This is also the main entry point for determining if an instruction is legal.
fn encode(&self,
dfg: &ir::DataFlowGraph,
inst: &ir::InstructionData,
ctrl_typevar: ir::Type)
-> Result<Encoding, Legalize> {
fn encode(
&self,
dfg: &ir::DataFlowGraph,
inst: &ir::InstructionData,
ctrl_typevar: ir::Type,
) -> Result<Encoding, Legalize> {
let mut iter = self.legal_encodings(dfg, inst, ctrl_typevar);
iter.next().ok_or_else(|| iter.legalize().into())
}
@@ -244,11 +246,13 @@ pub trait TargetIsa {
///
/// Note that this will call `put*` methods on the trait object via its vtable which is not the
/// fastest way of emitting code.
fn emit_inst(&self,
func: &ir::Function,
inst: ir::Inst,
divert: &mut regalloc::RegDiversions,
sink: &mut binemit::CodeSink);
fn emit_inst(
&self,
func: &ir::Function,
inst: ir::Inst,
divert: &mut regalloc::RegDiversions,
sink: &mut binemit::CodeSink,
);
/// Emit a whole function into memory.
///

31
lib/cretonne/src/isa/registers.rs
View File

@@ -74,24 +74,23 @@ impl RegBank {
/// Try to parse a regunit name. The name is not expected to begin with `%`.
fn parse_regunit(&self, name: &str) -> Option<RegUnit> {
match self.names.iter().position(|&x| x == name) {
Some(offset) => {
// This is one of the special-cased names.
Some(offset as RegUnit)
}
None => {
// Try a regular prefixed name.
if name.starts_with(self.prefix) {
name[self.prefix.len()..].parse().ok()
} else {
None
}
Some(offset) => {
// This is one of the special-cased names.
Some(offset as RegUnit)
}
None => {
// Try a regular prefixed name.
if name.starts_with(self.prefix) {
name[self.prefix.len()..].parse().ok()
} else {
None
}
}
.and_then(|offset| if offset < self.units {
Some(offset + self.first_unit)
} else {
None
})
}.and_then(|offset| if offset < self.units {
Some(offset + self.first_unit)
} else {
None
})
}
/// Write `regunit` to `w`, assuming that it belongs to this bank.

10
lib/cretonne/src/isa/riscv/abi.rs
View File

@@ -86,10 +86,12 @@ impl ArgAssigner for Args {
}
/// Legalize `sig` for RISC-V.
pub fn legalize_signature(sig: &mut ir::Signature,
flags: &shared_settings::Flags,
isa_flags: &settings::Flags,
current: bool) {
pub fn legalize_signature(
sig: &mut ir::Signature,
flags: &shared_settings::Flags,
isa_flags: &settings::Flags,
current: bool,
) {
let bits = if flags.is_64bit() { 64 } else { 32 };
let mut args = Args::new(bits, isa_flags.enable_e());

18
lib/cretonne/src/isa/riscv/binemit.rs
View File

@@ -29,11 +29,7 @@ impl Into<Reloc> for RelocKind {
/// 25 20 15 12 7 0
///
/// Encoding bits: `opcode[6:2] | (funct3 << 5) | (funct7 << 8)`.
fn put_r<CS: CodeSink + ?Sized>(bits: u16,
rs1: RegUnit,
rs2: RegUnit,
rd: RegUnit,
sink: &mut CS) {
fn put_r<CS: CodeSink + ?Sized>(bits: u16, rs1: RegUnit, rs2: RegUnit, rd: RegUnit, sink: &mut CS) {
let bits = bits as u32;
let opcode5 = bits & 0x1f;
let funct3 = (bits >> 5) & 0x7;
@@ -63,11 +59,13 @@ fn put_r<CS: CodeSink + ?Sized>(bits: u16,
/// Both funct7 and shamt contribute to bit 25. In RV64, shamt uses it for shifts > 31.
///
/// Encoding bits: `opcode[6:2] | (funct3 << 5) | (funct7 << 8)`.
fn put_rshamt<CS: CodeSink + ?Sized>(bits: u16,
rs1: RegUnit,
shamt: i64,
rd: RegUnit,
sink: &mut CS) {
fn put_rshamt<CS: CodeSink + ?Sized>(
bits: u16,
rs1: RegUnit,
shamt: i64,
rd: RegUnit,
sink: &mut CS,
) {
let bits = bits as u32;
let opcode5 = bits & 0x1f;
let funct3 = (bits >> 5) & 0x7;

60
lib/cretonne/src/isa/riscv/mod.rs
View File

@@ -29,19 +29,20 @@ pub fn isa_builder() -> IsaBuilder {
}
}
fn isa_constructor(shared_flags: shared_settings::Flags,
builder: &shared_settings::Builder)
-> Box<TargetIsa> {
fn isa_constructor(
shared_flags: shared_settings::Flags,
builder: &shared_settings::Builder,
) -> Box<TargetIsa> {
let level1 = if shared_flags.is_64bit() {
&enc_tables::LEVEL1_RV64[..]
} else {
&enc_tables::LEVEL1_RV32[..]
};
Box::new(Isa {
isa_flags: settings::Flags::new(&shared_flags, builder),
shared_flags,
cpumode: level1,
})
isa_flags: settings::Flags::new(&shared_flags, builder),
shared_flags,
cpumode: level1,
})
}
impl TargetIsa for Isa {
@@ -61,21 +62,24 @@ impl TargetIsa for Isa {
enc_tables::INFO.clone()
}
fn legal_encodings<'a>(&'a self,
dfg: &'a ir::DataFlowGraph,
inst: &'a ir::InstructionData,
ctrl_typevar: ir::Type)
-> Encodings<'a> {
lookup_enclist(ctrl_typevar,
inst,
dfg,
self.cpumode,
&enc_tables::LEVEL2[..],
&enc_tables::ENCLISTS[..],
&enc_tables::LEGALIZE_ACTIONS[..],
&enc_tables::RECIPE_PREDICATES[..],
&enc_tables::INST_PREDICATES[..],
self.isa_flags.predicate_view())
fn legal_encodings<'a>(
&'a self,
dfg: &'a ir::DataFlowGraph,
inst: &'a ir::InstructionData,
ctrl_typevar: ir::Type,
) -> Encodings<'a> {
lookup_enclist(
ctrl_typevar,
inst,
dfg,
self.cpumode,
&enc_tables::LEVEL2[..],
&enc_tables::ENCLISTS[..],
&enc_tables::LEGALIZE_ACTIONS[..],
&enc_tables::RECIPE_PREDICATES[..],
&enc_tables::INST_PREDICATES[..],
self.isa_flags.predicate_view(),
)
}
fn legalize_signature(&self, sig: &mut ir::Signature, current: bool) {
@@ -90,11 +94,13 @@ impl TargetIsa for Isa {
abi::allocatable_registers(func, &self.isa_flags)
}
fn emit_inst(&self,
func: &ir::Function,
inst: ir::Inst,
divert: &mut regalloc::RegDiversions,
sink: &mut CodeSink) {
fn emit_inst(
&self,
func: &ir::Function,
inst: ir::Inst,
divert: &mut regalloc::RegDiversions,
sink: &mut CodeSink,
) {
binemit::emit_inst(func, inst, divert, sink)
}

8
lib/cretonne/src/isa/riscv/settings.rs
View File

@@ -18,14 +18,16 @@ mod tests {
let shared = settings::Flags::new(&settings::builder());
let b = builder();
let f = Flags::new(&shared, &b);
assert_eq!(f.to_string(),
"[riscv]\n\
assert_eq!(
f.to_string(),
"[riscv]\n\
supports_m = false\n\
supports_a = false\n\
supports_f = false\n\
supports_d = false\n\
enable_m = true\n\
enable_e = false\n");
enable_e = false\n"
);
// Predicates are not part of the Display output.
assert_eq!(f.full_float(), false);
}