aarch64: Rework amode compilation to produce SSA code (#5369)

Rework the compilation of amodes in the aarch64 backend to stop reusing registers and instead generate fresh virtual registers for intermediates. This resolves some SSA checker violations with the aarch64 backend, and as a nice side-effect removes some unnecessary movs in the generated code.

cranelift/filetests/filetests/isa/aarch64/amodes.clif

@@ -53,9 +53,9 @@ block0(v0: i64, v1: i32):
 
 ; block0:
 ;   add x3, x0, #68
-;   add x3, x3, x0
-;   add x3, x3, x1, SXTW
-;   ldr w0, [x3, w1, SXTW]
+;   add x5, x3, x0
+;   add x7, x5, x1, SXTW
+;   ldr w0, [x7, w1, SXTW]
 ;   ret
 
 function %f9(i64, i64, i64) -> i32 {
@@ -69,10 +69,9 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   mov x5, x0
-;   add x5, x5, x2
-;   add x5, x5, x1
-;   ldr w0, [x5, #48]
+;   add x4, x0, x2
+;   add x6, x4, x1
+;   ldr w0, [x6, #48]
 ;   ret
 
 function %f10(i64, i64, i64) -> i32 {
@@ -86,10 +85,10 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movz x4, #4100
-;   add x4, x4, x1
-;   add x4, x4, x2
-;   ldr w0, [x4, x0]
+;   movz x5, #4100
+;   add x5, x5, x1
+;   add x8, x5, x2
+;   ldr w0, [x8, x0]
 ;   ret
 
 function %f10() -> i32 {
@@ -139,10 +138,10 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movz w2, #51712
-;   movk w2, w2, #15258, LSL #16
-;   add x2, x2, x0
-;   ldr w0, [x2]
+;   movz w3, #51712
+;   movk w3, w3, #15258, LSL #16
+;   add x4, x3, x0
+;   ldr w0, [x4]
 ;   ret
 
 function %f14(i32) -> i32 {
@@ -233,10 +232,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x6, x0
-;   mov x4, x6
-;   ldp x0, x1, [x4]
-;   mov x5, x6
+;   mov x5, x0
+;   ldp x0, x1, [x5]
 ;   stp x0, x1, [x5]
 ;   ret
 
@@ -248,10 +245,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x6, x0
-;   mov x4, x6
-;   ldp x0, x1, [x4, #16]
-;   mov x5, x6
+;   mov x5, x0
+;   ldp x0, x1, [x5, #16]
 ;   stp x0, x1, [x5, #16]
 ;   ret
 
@@ -263,10 +258,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x6, x0
-;   mov x4, x6
-;   ldp x0, x1, [x4, #504]
-;   mov x5, x6
+;   mov x5, x0
+;   ldp x0, x1, [x5, #504]
 ;   stp x0, x1, [x5, #504]
 ;   ret
 
@@ -278,10 +271,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x6, x0
-;   mov x4, x6
-;   ldp x0, x1, [x4, #-512]
-;   mov x5, x6
+;   mov x5, x0
+;   ldp x0, x1, [x5, #-512]
 ;   stp x0, x1, [x5, #-512]
 ;   ret
 
@@ -294,10 +285,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x6, x0
-;   mov x4, x6
-;   ldp x0, x1, [x4, #32]
-;   mov x5, x6
+;   mov x5, x0
+;   ldp x0, x1, [x5, #32]
 ;   stp x0, x1, [x5, #32]
 ;   ret
 
@@ -310,11 +299,11 @@ block0(v0: i32):
 }
 
 ; block0:
-;   sxtw x4, w0
-;   mov x11, x0
-;   ldp x0, x1, [x4]
-;   sxtw x5, w11
-;   stp x0, x1, [x5]
+;   sxtw x3, w0
+;   mov x8, x0
+;   ldp x0, x1, [x3]
+;   sxtw x4, w8
+;   stp x0, x1, [x4]
 ;   ret
 
 function %i128_32bit_sextend(i64, i32) -> i128 {
@@ -328,13 +317,11 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   mov x9, x0
-;   mov x5, x9
-;   add x5, x5, x1, SXTW
-;   mov x11, x1
-;   ldp x0, x1, [x5, #24]
-;   mov x7, x9
-;   add x7, x7, x11, SXTW
-;   stp x0, x1, [x7, #24]
+;   add x4, x0, x1, SXTW
+;   mov x11, x0
+;   mov x9, x1
+;   ldp x0, x1, [x4, #24]
+;   add x5, x11, x9, SXTW
+;   stp x0, x1, [x5, #24]
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/stack.clif

@@ -442,8 +442,8 @@ block0(v0: i128):
 ;   mov fp, sp
 ;   sub sp, sp, #16
 ; block0:
-;   mov x4, sp
-;   stp x0, x1, [x4]
+;   mov x3, sp
+;   stp x0, x1, [x3]
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
@@ -461,8 +461,8 @@ block0(v0: i128):
 ;   mov fp, sp
 ;   sub sp, sp, #32
 ; block0:
-;   add x4, sp, #32
-;   stp x0, x1, [x4]
+;   add x3, sp, #32
+;   stp x0, x1, [x3]
 ;   add sp, sp, #32
 ;   ldp fp, lr, [sp], #16
 ;   ret
@@ -482,8 +482,8 @@ block0(v0: i128):
 ;   movk w16, w16, #1, LSL #16
 ;   sub sp, sp, x16, UXTX
 ; block0:
-;   mov x4, sp
-;   stp x0, x1, [x4]
+;   mov x3, sp
+;   stp x0, x1, [x3]
 ;   movz w16, #34480
 ;   movk w16, w16, #1, LSL #16
 ;   add sp, sp, x16, UXTX
@@ -502,8 +502,8 @@ block0:
 ;   mov fp, sp
 ;   sub sp, sp, #16
 ; block0:
-;   mov x3, sp
-;   ldp x0, x1, [x3]
+;   mov x2, sp
+;   ldp x0, x1, [x2]
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
@@ -521,8 +521,8 @@ block0:
 ;   mov fp, sp
 ;   sub sp, sp, #32
 ; block0:
-;   add x3, sp, #32
-;   ldp x0, x1, [x3]
+;   add x2, sp, #32
+;   ldp x0, x1, [x2]
 ;   add sp, sp, #32
 ;   ldp fp, lr, [sp], #16
 ;   ret
@@ -542,8 +542,8 @@ block0:
 ;   movk w16, w16, #1, LSL #16
 ;   sub sp, sp, x16, UXTX
 ; block0:
-;   mov x3, sp
-;   ldp x0, x1, [x3]
+;   mov x2, sp
+;   ldp x0, x1, [x2]
 ;   movz w16, #34480
 ;   movk w16, w16, #1, LSL #16
 ;   add sp, sp, x16, UXTX