Rework/simplify unwind infrastructure and implement Windows unwind.

Our previous implementation of unwind infrastructure was somewhat
complex and brittle: it parsed generated instructions in order to
reverse-engineer unwind info from prologues. It also relied on some
fragile linkage to communicate instruction-layout information that VCode
was not designed to provide.

A much simpler, more reliable, and easier-to-reason-about approach is to
embed unwind directives as pseudo-instructions in the prologue as we
generate it. That way, we can say what we mean and just emit it
directly.

The usual reasoning that leads to the reverse-engineering approach is
that metadata is hard to keep in sync across optimization passes; but
here, (i) prologues are generated at the very end of the pipeline, and
(ii) if we ever do a post-prologue-gen optimization, we can treat unwind
directives as black boxes with unknown side-effects, just as we do for
some other pseudo-instructions today.

It turns out that it was easier to just build this for both x64 and
aarch64 (since they share a factored-out ABI implementation), and wire
up the platform-specific unwind-info generation for Windows and SystemV.
Now we have simpler unwind on all platforms and we can delete the old
unwind infra as soon as we remove the old backend.

There were a few consequences to supporting Fastcall unwind in
particular that led to a refactor of the common ABI. Windows only
supports naming clobbered-register save locations within 240 bytes of
the frame-pointer register, whatever one chooses that to be (RSP or
RBP). We had previously saved clobbers below the fixed frame (and below
nominal-SP). The 240-byte range has to include the old RBP too, so we're
forced to place clobbers at the top of the frame, just below saved
RBP/RIP. This is fine; we always keep a frame pointer anyway because we
use it to refer to stack args. It does mean that offsets of fixed-frame
slots (spillslots, stackslots) from RBP are no longer known before we do
regalloc, so if we ever want to index these off of RBP rather than
nominal-SP because we add support for `alloca` (dynamic frame growth),
then we'll need a "nominal-BP" mode that is resolved after regalloc and
clobber-save code is generated. I added a comment to this effect in
`abi_impl.rs`.

The above refactor touched both x64 and aarch64 because of shared code.
This had a further effect in that the old aarch64 prologue generation
subtracted from `sp` once to allocate space, then used stores to `[sp,
offset]` to save clobbers. Unfortunately the offset only has 7-bit
range, so if there are enough clobbered registers (and there can be --
aarch64 has 384 bytes of registers; at least one unit test hits this)
the stores/loads will be out-of-range. I really don't want to synthesize
large-offset sequences here; better to go back to the simpler
pre-index/post-index `stp r1, r2, [sp, #-16]` form that works just like
a "push". It's likely not much worse microarchitecturally (dependence
chain on SP, but oh well) and it actually saves an instruction if
there's no other frame to allocate. As a further advantage, it's much
simpler to understand; simpler is usually better.

This PR adds the new backend on Windows to CI as well.

cranelift/codegen/src/isa/unwind/systemv.rs

@@ -1,6 +1,8 @@
 //! System V ABI unwind information.
 
+use crate::binemit::CodeOffset;
 use crate::isa::unwind::input;
+use crate::isa::unwind::UnwindInst;
 use crate::result::{CodegenError, CodegenResult};
 use alloc::vec::Vec;
 use gimli::write::{Address, FrameDescriptionEntry};
@@ -100,6 +102,16 @@ pub(crate) trait RegisterMapper<Reg> {
     fn map(&self, reg: Reg) -> Result<Register, RegisterMappingError>;
     /// Gets stack pointer register.
     fn sp(&self) -> Register;
+    /// Gets the frame pointer register.
+    fn fp(&self) -> Register;
+    /// Gets the link register, if any.
+    fn lr(&self) -> Option<Register> {
+        None
+    }
+    /// What is the offset from saved FP to saved LR?
+    fn lr_offset(&self) -> Option<u32> {
+        None
+    }
 }
 
 /// Represents unwind information for a single System V ABI function.
@@ -112,7 +124,82 @@ pub struct UnwindInfo {
     len: u32,
 }
 
+pub(crate) fn create_unwind_info_from_insts<MR: RegisterMapper<regalloc::Reg>>(
+    insts: &[(CodeOffset, UnwindInst)],
+    code_len: usize,
+    mr: &MR,
+) -> CodegenResult<UnwindInfo> {
+    let mut instructions = vec![];
+
+    let mut clobber_offset_to_cfa = 0;
+    for &(instruction_offset, ref inst) in insts {
+        match inst {
+            &UnwindInst::PushFrameRegs {
+                offset_upward_to_caller_sp,
+            } => {
+                // Define CFA in terms of current SP (SP changed and we haven't
+                // set FP yet).
+                instructions.push((
+                    instruction_offset,
+                    CallFrameInstruction::CfaOffset(offset_upward_to_caller_sp as i32),
+                ));
+                // Note that we saved the old FP value on the stack.
+                instructions.push((
+                    instruction_offset,
+                    CallFrameInstruction::Offset(mr.fp(), -(offset_upward_to_caller_sp as i32)),
+                ));
+                // If there is a link register on this architecture, note that
+                // we saved it as well.
+                if let Some(lr) = mr.lr() {
+                    instructions.push((
+                        instruction_offset,
+                        CallFrameInstruction::Offset(
+                            lr,
+                            -(offset_upward_to_caller_sp as i32)
+                                + mr.lr_offset().expect("LR offset not provided") as i32,
+                        ),
+                    ));
+                }
+            }
+            &UnwindInst::DefineNewFrame {
+                offset_upward_to_caller_sp,
+                offset_downward_to_clobbers,
+            } => {
+                // Define CFA in terms of FP. Note that we assume it was already
+                // defined correctly in terms of the current SP, and FP has just
+                // been set to the current SP, so we do not need to change the
+                // offset, only the register.
+                instructions.push((
+                    instruction_offset,
+                    CallFrameInstruction::CfaRegister(mr.fp()),
+                ));
+                // Record distance from CFA downward to clobber area so we can
+                // express clobber offsets later in terms of CFA.
+                clobber_offset_to_cfa = offset_upward_to_caller_sp + offset_downward_to_clobbers;
+            }
+            &UnwindInst::SaveReg {
+                clobber_offset,
+                reg,
+            } => {
+                let reg = mr
+                    .map(reg.to_reg())
+                    .map_err(|e| CodegenError::RegisterMappingError(e))?;
+                let off = (clobber_offset as i32) - (clobber_offset_to_cfa as i32);
+                instructions.push((instruction_offset, CallFrameInstruction::Offset(reg, off)));
+            }
+        }
+    }
+
+    Ok(UnwindInfo {
+        instructions,
+        len: code_len as u32,
+    })
+}
+
 impl UnwindInfo {
+    // TODO: remove `build()` below when old backend is removed. The new backend uses a simpler
+    // approach in `create_unwind_info_from_insts()` above.
+
     pub(crate) fn build<'b, Reg: PartialEq + Copy>(
         unwind: input::UnwindInfo<Reg>,
         map_reg: &'b dyn RegisterMapper<Reg>,
@@ -179,6 +266,8 @@ impl UnwindInfo {
     }
 }
 
+// TODO: delete the builder below when the old backend is removed.
+
 struct InstructionBuilder<'a, Reg: PartialEq + Copy> {
     sp_offset: i32,
     frame_register: Option<Reg>,