ISLE: Rename {gpr,xmm}_mem_new constructors to reg_mem_to_{gpr,xmm}_mem

cranelift/codegen/src/isa/x64/inst.isle

@@ -876,8 +876,8 @@
 ;; Construct a new `XmmMem` from the given `RegMem`.
 ;;
 ;; Asserts that the `RegMem`'s register, if any, is an XMM register.
-(decl xmm_mem_new (RegMem) XmmMem)
+(decl reg_mem_to_xmm_mem (RegMem) XmmMem)
-(extern constructor xmm_mem_new xmm_mem_new)
+(extern constructor reg_mem_to_xmm_mem reg_mem_to_xmm_mem)
 
 ;; Construct a new `GprMemImm` from the given `RegMemImm`.
 ;;
@@ -918,8 +918,8 @@
 ;; Construct a new `GprMem` from a `RegMem`.
 ;;
 ;; Asserts that the `RegMem`'s register, if any, is a GPR.
-(decl gpr_mem_new (RegMem) GprMem)
+(decl reg_mem_to_gpr_mem (RegMem) GprMem)
-(extern constructor gpr_mem_new gpr_mem_new)
+(extern constructor reg_mem_to_gpr_mem reg_mem_to_gpr_mem)
 
 ;; Construct a `GprMem` from a `Reg`.
 ;;
@@ -939,7 +939,7 @@
 ;; Asserts that the value goes into a GPR.
 (decl put_in_gpr_mem (Value) GprMem)
 (rule (put_in_gpr_mem val)
-      (gpr_mem_new (put_in_reg_mem val)))
+      (reg_mem_to_gpr_mem (put_in_reg_mem val)))
 
 ;; Put a value into a `GprMemImm`.
 ;;
@@ -960,7 +960,7 @@
 ;; Asserts that the value goes into a XMM.
 (decl put_in_xmm_mem (Value) XmmMem)
 (rule (put_in_xmm_mem val)
-      (xmm_mem_new (put_in_reg_mem val)))
+      (reg_mem_to_xmm_mem (put_in_reg_mem val)))
 
 ;; Put a value into a `XmmMemImm`.
 ;;
@@ -1177,23 +1177,23 @@
 
 (rule (x64_load $F32 addr _ext_kind)
       (xmm_to_reg (xmm_unary_rm_r (SseOpcode.Movss)
-                                  (xmm_mem_new (synthetic_amode_to_reg_mem addr)))))
+                                  (reg_mem_to_xmm_mem (synthetic_amode_to_reg_mem addr)))))
 
 (rule (x64_load $F64 addr _ext_kind)
       (xmm_to_reg (xmm_unary_rm_r (SseOpcode.Movsd)
-                                  (xmm_mem_new (synthetic_amode_to_reg_mem addr)))))
+                                  (reg_mem_to_xmm_mem (synthetic_amode_to_reg_mem addr)))))
 
 (rule (x64_load $F32X4 addr _ext_kind)
       (xmm_to_reg (xmm_unary_rm_r (SseOpcode.Movups)
-                                  (xmm_mem_new (synthetic_amode_to_reg_mem addr)))))
+                                  (reg_mem_to_xmm_mem (synthetic_amode_to_reg_mem addr)))))
 
 (rule (x64_load $F64X2 addr _ext_kind)
       (xmm_to_reg (xmm_unary_rm_r (SseOpcode.Movupd)
-                                  (xmm_mem_new (synthetic_amode_to_reg_mem addr)))))
+                                  (reg_mem_to_xmm_mem (synthetic_amode_to_reg_mem addr)))))
 
 (rule (x64_load (multi_lane _bits _lanes) addr _ext_kind)
       (xmm_to_reg (xmm_unary_rm_r (SseOpcode.Movdqu)
-                                  (xmm_mem_new (synthetic_amode_to_reg_mem addr)))))
+                                  (reg_mem_to_xmm_mem (synthetic_amode_to_reg_mem addr)))))
 
 ;;;; Instruction Constructors ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
@@ -1317,13 +1317,13 @@
 ;; `f32` immediates.
 (rule (imm $F32 bits)
       (xmm_to_reg (gpr_to_xmm (SseOpcode.Movd)
-                              (gpr_mem_new (RegMem.Reg (imm $I32 bits)))
+                              (reg_mem_to_gpr_mem (RegMem.Reg (imm $I32 bits)))
                               (OperandSize.Size32))))
 
 ;; `f64` immediates.
 (rule (imm $F64 bits)
       (xmm_to_reg (gpr_to_xmm (SseOpcode.Movq)
-                              (gpr_mem_new (RegMem.Reg (imm $I64 bits)))
+                              (reg_mem_to_gpr_mem (RegMem.Reg (imm $I64 bits)))
                               (OperandSize.Size64))))
 
 (decl nonzero_u64_fits_in_u32 (u64) u64)

cranelift/codegen/src/isa/x64/lower.isle

@@ -591,7 +591,7 @@
             (unmasked Xmm (psllw src_ amt_xmm))
             (mask_addr SyntheticAmode (ishl_i8x16_mask amt_gpr))
             (mask Reg (x64_load $I8X16 mask_addr (ExtKind.None))))
-        (value_xmm (sse_and $I8X16 unmasked (xmm_mem_new (RegMem.Reg mask))))))
+        (value_xmm (sse_and $I8X16 unmasked (reg_mem_to_xmm_mem (RegMem.Reg mask))))))
 
 ;; Get the address of the mask to use when fixing up the lanes that weren't
 ;; correctly generated by the 16x8 shift.
@@ -690,7 +690,7 @@
             (mask Reg (x64_load $I8X16 mask_addr (ExtKind.None))))
         (value_xmm (sse_and $I8X16
                             unmasked
-                            (xmm_mem_new (RegMem.Reg mask))))))
+                            (reg_mem_to_xmm_mem (RegMem.Reg mask))))))
 
 ;; Get the address of the mask to use when fixing up the lanes that weren't
 ;; correctly generated by the 16x8 shift.
@@ -837,8 +837,8 @@
             (amt_ Imm8Reg (put_masked_in_imm8_reg amt $I64))
             (shifted_lo Reg (sar $I64 (gpr_to_reg lo) amt_))
             (shifted_hi Reg (sar $I64 (gpr_to_reg hi) amt_)))
-        (value_xmm (make_i64x2_from_lanes (gpr_mem_new (RegMem.Reg shifted_lo))
+        (value_xmm (make_i64x2_from_lanes (reg_mem_to_gpr_mem (RegMem.Reg shifted_lo))
-                                          (gpr_mem_new (RegMem.Reg shifted_hi))))))
+                                          (reg_mem_to_gpr_mem (RegMem.Reg shifted_hi))))))
 
 ;;;; Rules for `rotl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -1363,23 +1363,23 @@
 
 ;; i8x16.replace_lane
 (rule (vec_insert_lane $I8X16 vec val idx)
-      (pinsrb vec (gpr_mem_new val) idx))
+      (pinsrb vec (reg_mem_to_gpr_mem val) idx))
 
 ;; i16x8.replace_lane
 (rule (vec_insert_lane $I16X8 vec val idx)
-      (pinsrw vec (gpr_mem_new val) idx))
+      (pinsrw vec (reg_mem_to_gpr_mem val) idx))
 
 ;; i32x4.replace_lane
 (rule (vec_insert_lane $I32X4 vec val idx)
-      (pinsrd vec (gpr_mem_new val) idx (OperandSize.Size32)))
+      (pinsrd vec (reg_mem_to_gpr_mem val) idx (OperandSize.Size32)))
 
 ;; i64x2.replace_lane
 (rule (vec_insert_lane $I64X2 vec val idx)
-      (pinsrd vec (gpr_mem_new val) idx (OperandSize.Size64)))
+      (pinsrd vec (reg_mem_to_gpr_mem val) idx (OperandSize.Size64)))
 
 ;; f32x4.replace_lane
 (rule (vec_insert_lane $F32X4 vec val idx)
-      (insertps vec (xmm_mem_new val) (sse_insertps_lane_imm idx)))
+      (insertps vec (reg_mem_to_xmm_mem val) (sse_insertps_lane_imm idx)))
 
 ;; External rust code used to calculate the immediate value to `insertps`.
 (decl sse_insertps_lane_imm (u8) u8)
@@ -1401,10 +1401,10 @@
 ;; internally as `xmm_rm_r` will merge the temp register into our `vec`
 ;; register.
 (rule (vec_insert_lane $F64X2 vec (RegMem.Reg val) 0)
-      (movsd vec (xmm_mem_new (RegMem.Reg val))))
+      (movsd vec (reg_mem_to_xmm_mem (RegMem.Reg val))))
 (rule (vec_insert_lane $F64X2 vec mem 0)
       (movsd vec (xmm_to_xmm_mem (xmm_unary_rm_r (SseOpcode.Movsd)
-                                                 (xmm_mem_new mem)))))
+                                                 (reg_mem_to_xmm_mem mem)))))
 
 ;; f64x2.replace_lane 1
 ;;
@@ -1412,7 +1412,7 @@
 ;; into the second lane where unlike above cases we're not using the lane
 ;; immediate as an immediate to the instruction itself.
 (rule (vec_insert_lane $F64X2 vec val 1)
-      (movlhps vec (xmm_mem_new val)))
+      (movlhps vec (reg_mem_to_xmm_mem val)))
 
 ;;;; Rules for `imax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 

cranelift/codegen/src/isa/x64/lower/isle.rs

@@ -360,7 +360,7 @@ where
     }
 
     #[inline]
-    fn xmm_mem_new(&mut self, rm: &RegMem) -> XmmMem {
+    fn reg_mem_to_xmm_mem(&mut self, rm: &RegMem) -> XmmMem {
         XmmMem::new(rm.clone()).unwrap()
     }
 
@@ -400,7 +400,7 @@ where
     }
 
     #[inline]
-    fn gpr_mem_new(&mut self, rm: &RegMem) -> GprMem {
+    fn reg_mem_to_gpr_mem(&mut self, rm: &RegMem) -> GprMem {
         GprMem::new(rm.clone()).unwrap()
     }
 

cranelift/codegen/src/isa/x64/lower/isle/generated_code.manifest

@@ -1,4 +1,4 @@
 src/clif.isle 9ea75a6f790b5c03
 src/prelude.isle 6aaf8ce0f5a5c2ec
-src/isa/x64/inst.isle 2f76eb1f9ecf0c5e
+src/isa/x64/inst.isle 7513533d16948249
-src/isa/x64/lower.isle 144c33c4e64a17a7
+src/isa/x64/lower.isle ccda13e9fe83c89a

cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs

@@ -84,7 +84,7 @@ pub trait Context {
     fn xmm_to_xmm_mem_imm(&mut self, arg0: Xmm) -> XmmMemImm;
     fn temp_writable_gpr(&mut self) -> WritableGpr;
     fn temp_writable_xmm(&mut self) -> WritableXmm;
-    fn xmm_mem_new(&mut self, arg0: &RegMem) -> XmmMem;
+    fn reg_mem_to_xmm_mem(&mut self, arg0: &RegMem) -> XmmMem;
     fn gpr_mem_imm_new(&mut self, arg0: &RegMemImm) -> GprMemImm;
     fn xmm_mem_imm_new(&mut self, arg0: &RegMemImm) -> XmmMemImm;
     fn xmm_to_xmm_mem(&mut self, arg0: Xmm) -> XmmMem;
@@ -92,7 +92,7 @@ pub trait Context {
     fn gpr_mem_to_reg_mem(&mut self, arg0: &GprMem) -> RegMem;
     fn xmm_new(&mut self, arg0: Reg) -> Xmm;
     fn gpr_new(&mut self, arg0: Reg) -> Gpr;
-    fn gpr_mem_new(&mut self, arg0: &RegMem) -> GprMem;
+    fn reg_mem_to_gpr_mem(&mut self, arg0: &RegMem) -> GprMem;
     fn reg_to_gpr_mem(&mut self, arg0: Reg) -> GprMem;
     fn xmm0(&mut self) -> WritableXmm;
     fn avx512vl_enabled(&mut self, arg0: Type) -> Option<()>;
@@ -639,7 +639,7 @@ pub fn constructor_put_in_gpr_mem<C: Context>(ctx: &mut C, arg0: Value) -> Optio
     let pattern0_0 = arg0;
     // Rule at src/isa/x64/inst.isle line 941.
     let expr0_0 = C::put_in_reg_mem(ctx, pattern0_0);
-    let expr1_0 = C::gpr_mem_new(ctx, &expr0_0);
+    let expr1_0 = C::reg_mem_to_gpr_mem(ctx, &expr0_0);
     return Some(expr1_0);
 }
 
@@ -666,7 +666,7 @@ pub fn constructor_put_in_xmm_mem<C: Context>(ctx: &mut C, arg0: Value) -> Optio
     let pattern0_0 = arg0;
     // Rule at src/isa/x64/inst.isle line 962.
     let expr0_0 = C::put_in_reg_mem(ctx, pattern0_0);
-    let expr1_0 = C::xmm_mem_new(ctx, &expr0_0);
+    let expr1_0 = C::reg_mem_to_xmm_mem(ctx, &expr0_0);
     return Some(expr1_0);
 }
 
@@ -970,7 +970,7 @@ pub fn constructor_x64_load<C: Context>(
         // Rule at src/isa/x64/inst.isle line 1178.
         let expr0_0 = SseOpcode::Movss;
         let expr1_0 = C::synthetic_amode_to_reg_mem(ctx, pattern2_0);
-        let expr2_0 = C::xmm_mem_new(ctx, &expr1_0);
+        let expr2_0 = C::reg_mem_to_xmm_mem(ctx, &expr1_0);
         let expr3_0 = constructor_xmm_unary_rm_r(ctx, &expr0_0, &expr2_0)?;
         let expr4_0 = C::xmm_to_reg(ctx, expr3_0);
         return Some(expr4_0);
@@ -981,7 +981,7 @@ pub fn constructor_x64_load<C: Context>(
         // Rule at src/isa/x64/inst.isle line 1182.
         let expr0_0 = SseOpcode::Movsd;
         let expr1_0 = C::synthetic_amode_to_reg_mem(ctx, pattern2_0);
-        let expr2_0 = C::xmm_mem_new(ctx, &expr1_0);
+        let expr2_0 = C::reg_mem_to_xmm_mem(ctx, &expr1_0);
         let expr3_0 = constructor_xmm_unary_rm_r(ctx, &expr0_0, &expr2_0)?;
         let expr4_0 = C::xmm_to_reg(ctx, expr3_0);
         return Some(expr4_0);
@@ -992,7 +992,7 @@ pub fn constructor_x64_load<C: Context>(
         // Rule at src/isa/x64/inst.isle line 1186.
         let expr0_0 = SseOpcode::Movups;
         let expr1_0 = C::synthetic_amode_to_reg_mem(ctx, pattern2_0);
-        let expr2_0 = C::xmm_mem_new(ctx, &expr1_0);
+        let expr2_0 = C::reg_mem_to_xmm_mem(ctx, &expr1_0);
         let expr3_0 = constructor_xmm_unary_rm_r(ctx, &expr0_0, &expr2_0)?;
         let expr4_0 = C::xmm_to_reg(ctx, expr3_0);
         return Some(expr4_0);
@@ -1003,7 +1003,7 @@ pub fn constructor_x64_load<C: Context>(
         // Rule at src/isa/x64/inst.isle line 1190.
         let expr0_0 = SseOpcode::Movupd;
         let expr1_0 = C::synthetic_amode_to_reg_mem(ctx, pattern2_0);
-        let expr2_0 = C::xmm_mem_new(ctx, &expr1_0);
+        let expr2_0 = C::reg_mem_to_xmm_mem(ctx, &expr1_0);
         let expr3_0 = constructor_xmm_unary_rm_r(ctx, &expr0_0, &expr2_0)?;
         let expr4_0 = C::xmm_to_reg(ctx, expr3_0);
         return Some(expr4_0);
@@ -1014,7 +1014,7 @@ pub fn constructor_x64_load<C: Context>(
         // Rule at src/isa/x64/inst.isle line 1194.
         let expr0_0 = SseOpcode::Movdqu;
         let expr1_0 = C::synthetic_amode_to_reg_mem(ctx, pattern2_0);
-        let expr2_0 = C::xmm_mem_new(ctx, &expr1_0);
+        let expr2_0 = C::reg_mem_to_xmm_mem(ctx, &expr1_0);
         let expr3_0 = constructor_xmm_unary_rm_r(ctx, &expr0_0, &expr2_0)?;
         let expr4_0 = C::xmm_to_reg(ctx, expr3_0);
         return Some(expr4_0);
@@ -1317,7 +1317,7 @@ pub fn constructor_imm<C: Context>(ctx: &mut C, arg0: Type, arg1: u64) -> Option
         let expr1_0: Type = I32;
         let expr2_0 = constructor_imm(ctx, expr1_0, pattern2_0)?;
         let expr3_0 = RegMem::Reg { reg: expr2_0 };
-        let expr4_0 = C::gpr_mem_new(ctx, &expr3_0);
+        let expr4_0 = C::reg_mem_to_gpr_mem(ctx, &expr3_0);
         let expr5_0 = OperandSize::Size32;
         let expr6_0 = constructor_gpr_to_xmm(ctx, &expr0_0, &expr4_0, &expr5_0)?;
         let expr7_0 = C::xmm_to_reg(ctx, expr6_0);
@@ -1346,7 +1346,7 @@ pub fn constructor_imm<C: Context>(ctx: &mut C, arg0: Type, arg1: u64) -> Option
         let expr1_0: Type = I64;
         let expr2_0 = constructor_imm(ctx, expr1_0, pattern2_0)?;
         let expr3_0 = RegMem::Reg { reg: expr2_0 };
-        let expr4_0 = C::gpr_mem_new(ctx, &expr3_0);
+        let expr4_0 = C::reg_mem_to_gpr_mem(ctx, &expr3_0);
         let expr5_0 = OperandSize::Size64;
         let expr6_0 = constructor_gpr_to_xmm(ctx, &expr0_0, &expr4_0, &expr5_0)?;
         let expr7_0 = C::xmm_to_reg(ctx, expr6_0);
@@ -3456,7 +3456,7 @@ pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<ValueReg
                             let expr7_0 = constructor_x64_load(ctx, expr5_0, &expr4_0, &expr6_0)?;
                             let expr8_0: Type = I8X16;
                             let expr9_0 = RegMem::Reg { reg: expr7_0 };
-                            let expr10_0 = C::xmm_mem_new(ctx, &expr9_0);
+                            let expr10_0 = C::reg_mem_to_xmm_mem(ctx, &expr9_0);
                             let expr11_0 = constructor_sse_and(ctx, expr8_0, expr3_0, &expr10_0)?;
                             let expr12_0 = constructor_value_xmm(ctx, expr11_0)?;
                             return Some(expr12_0);
@@ -3475,7 +3475,7 @@ pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<ValueReg
                             let expr7_0 = constructor_x64_load(ctx, expr5_0, &expr4_0, &expr6_0)?;
                             let expr8_0: Type = I8X16;
                             let expr9_0 = RegMem::Reg { reg: expr7_0 };
-                            let expr10_0 = C::xmm_mem_new(ctx, &expr9_0);
+                            let expr10_0 = C::reg_mem_to_xmm_mem(ctx, &expr9_0);
                             let expr11_0 = constructor_sse_and(ctx, expr8_0, expr3_0, &expr10_0)?;
                             let expr12_0 = constructor_value_xmm(ctx, expr11_0)?;
                             return Some(expr12_0);
@@ -3808,9 +3808,9 @@ pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<ValueReg
                             let expr13_0 = C::gpr_to_reg(ctx, expr6_0);
                             let expr14_0 = constructor_sar(ctx, expr12_0, expr13_0, &expr8_0)?;
                             let expr15_0 = RegMem::Reg { reg: expr11_0 };
-                            let expr16_0 = C::gpr_mem_new(ctx, &expr15_0);
+                            let expr16_0 = C::reg_mem_to_gpr_mem(ctx, &expr15_0);
                             let expr17_0 = RegMem::Reg { reg: expr14_0 };
-                            let expr18_0 = C::gpr_mem_new(ctx, &expr17_0);
+                            let expr18_0 = C::reg_mem_to_gpr_mem(ctx, &expr17_0);
                             let expr19_0 =
                                 constructor_make_i64x2_from_lanes(ctx, &expr16_0, &expr18_0)?;
                             let expr20_0 = constructor_value_xmm(ctx, expr19_0)?;
@@ -6152,7 +6152,7 @@ pub fn constructor_vec_insert_lane<C: Context>(
         let pattern3_0 = arg2;
         let pattern4_0 = arg3;
         // Rule at src/isa/x64/lower.isle line 1365.
-        let expr0_0 = C::gpr_mem_new(ctx, pattern3_0);
+        let expr0_0 = C::reg_mem_to_gpr_mem(ctx, pattern3_0);
         let expr1_0 = constructor_pinsrb(ctx, pattern2_0, &expr0_0, pattern4_0)?;
         return Some(expr1_0);
     }
@@ -6161,7 +6161,7 @@ pub fn constructor_vec_insert_lane<C: Context>(
         let pattern3_0 = arg2;
         let pattern4_0 = arg3;
         // Rule at src/isa/x64/lower.isle line 1369.
-        let expr0_0 = C::gpr_mem_new(ctx, pattern3_0);
+        let expr0_0 = C::reg_mem_to_gpr_mem(ctx, pattern3_0);
         let expr1_0 = constructor_pinsrw(ctx, pattern2_0, &expr0_0, pattern4_0)?;
         return Some(expr1_0);
     }
@@ -6170,7 +6170,7 @@ pub fn constructor_vec_insert_lane<C: Context>(
         let pattern3_0 = arg2;
         let pattern4_0 = arg3;
         // Rule at src/isa/x64/lower.isle line 1373.
-        let expr0_0 = C::gpr_mem_new(ctx, pattern3_0);
+        let expr0_0 = C::reg_mem_to_gpr_mem(ctx, pattern3_0);
         let expr1_0 = OperandSize::Size32;
         let expr2_0 = constructor_pinsrd(ctx, pattern2_0, &expr0_0, pattern4_0, &expr1_0)?;
         return Some(expr2_0);
@@ -6180,7 +6180,7 @@ pub fn constructor_vec_insert_lane<C: Context>(
         let pattern3_0 = arg2;
         let pattern4_0 = arg3;
         // Rule at src/isa/x64/lower.isle line 1377.
-        let expr0_0 = C::gpr_mem_new(ctx, pattern3_0);
+        let expr0_0 = C::reg_mem_to_gpr_mem(ctx, pattern3_0);
         let expr1_0 = OperandSize::Size64;
         let expr2_0 = constructor_pinsrd(ctx, pattern2_0, &expr0_0, pattern4_0, &expr1_0)?;
         return Some(expr2_0);
@@ -6190,7 +6190,7 @@ pub fn constructor_vec_insert_lane<C: Context>(
         let pattern3_0 = arg2;
         let pattern4_0 = arg3;
         // Rule at src/isa/x64/lower.isle line 1381.
-        let expr0_0 = C::xmm_mem_new(ctx, pattern3_0);
+        let expr0_0 = C::reg_mem_to_xmm_mem(ctx, pattern3_0);
         let expr1_0 = C::sse_insertps_lane_imm(ctx, pattern4_0);
         let expr2_0 = constructor_insertps(ctx, pattern2_0, &expr0_0, expr1_0)?;
         return Some(expr2_0);
@@ -6203,7 +6203,7 @@ pub fn constructor_vec_insert_lane<C: Context>(
             if pattern5_0 == 0 {
                 // Rule at src/isa/x64/lower.isle line 1403.
                 let expr0_0 = RegMem::Reg { reg: pattern4_0 };
-                let expr1_0 = C::xmm_mem_new(ctx, &expr0_0);
+                let expr1_0 = C::reg_mem_to_xmm_mem(ctx, &expr0_0);
                 let expr2_0 = constructor_movsd(ctx, pattern2_0, &expr1_0)?;
                 return Some(expr2_0);
             }
@@ -6212,7 +6212,7 @@ pub fn constructor_vec_insert_lane<C: Context>(
         if pattern4_0 == 0 {
             // Rule at src/isa/x64/lower.isle line 1405.
             let expr0_0 = SseOpcode::Movsd;
-            let expr1_0 = C::xmm_mem_new(ctx, pattern3_0);
+            let expr1_0 = C::reg_mem_to_xmm_mem(ctx, pattern3_0);
             let expr2_0 = constructor_xmm_unary_rm_r(ctx, &expr0_0, &expr1_0)?;
             let expr3_0 = C::xmm_to_xmm_mem(ctx, expr2_0);
             let expr4_0 = constructor_movsd(ctx, pattern2_0, &expr3_0)?;
@@ -6220,7 +6220,7 @@ pub fn constructor_vec_insert_lane<C: Context>(
         }
         if pattern4_0 == 1 {
             // Rule at src/isa/x64/lower.isle line 1414.
-            let expr0_0 = C::xmm_mem_new(ctx, pattern3_0);
+            let expr0_0 = C::reg_mem_to_xmm_mem(ctx, pattern3_0);
             let expr1_0 = constructor_movlhps(ctx, pattern2_0, &expr0_0)?;
             return Some(expr1_0);
         }