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ISLE: Rename {gpr,xmm}_mem_new constructors to reg_mem_to_{gpr,xmm}_mem

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This commit is contained in:
Nick Fitzgerald
2022-02-03 11:31:53 -08:00
parent 795b0aaf9a
commit 2c77cf866a
5 changed files with 52 additions and 52 deletions
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24
cranelift/codegen/src/isa/x64/lower.isle
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@@ -591,7 +591,7 @@
(unmasked Xmm (psllw src_ amt_xmm))
(mask_addr SyntheticAmode (ishl_i8x16_mask amt_gpr))
(mask Reg (x64_load $I8X16 mask_addr (ExtKind.None))))
(value_xmm (sse_and $I8X16 unmasked (xmm_mem_new (RegMem.Reg mask))))))
(value_xmm (sse_and $I8X16 unmasked (reg_mem_to_xmm_mem (RegMem.Reg mask))))))
;; Get the address of the mask to use when fixing up the lanes that weren't
;; correctly generated by the 16x8 shift.
@@ -690,7 +690,7 @@
(mask Reg (x64_load $I8X16 mask_addr (ExtKind.None))))
(value_xmm (sse_and $I8X16
unmasked
(xmm_mem_new (RegMem.Reg mask))))))
(reg_mem_to_xmm_mem (RegMem.Reg mask))))))
;; Get the address of the mask to use when fixing up the lanes that weren't
;; correctly generated by the 16x8 shift.
@@ -837,8 +837,8 @@
(amt_ Imm8Reg (put_masked_in_imm8_reg amt $I64))
(shifted_lo Reg (sar $I64 (gpr_to_reg lo) amt_))
(shifted_hi Reg (sar $I64 (gpr_to_reg hi) amt_)))
(value_xmm (make_i64x2_from_lanes (gpr_mem_new (RegMem.Reg shifted_lo))
(gpr_mem_new (RegMem.Reg shifted_hi))))))
(value_xmm (make_i64x2_from_lanes (reg_mem_to_gpr_mem (RegMem.Reg shifted_lo))
(reg_mem_to_gpr_mem (RegMem.Reg shifted_hi))))))
;;;; Rules for `rotl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -1363,23 +1363,23 @@
;; i8x16.replace_lane
(rule (vec_insert_lane $I8X16 vec val idx)
(pinsrb vec (gpr_mem_new val) idx))
(pinsrb vec (reg_mem_to_gpr_mem val) idx))
;; i16x8.replace_lane
(rule (vec_insert_lane $I16X8 vec val idx)
(pinsrw vec (gpr_mem_new val) idx))
(pinsrw vec (reg_mem_to_gpr_mem val) idx))
;; i32x4.replace_lane
(rule (vec_insert_lane $I32X4 vec val idx)
(pinsrd vec (gpr_mem_new val) idx (OperandSize.Size32)))
(pinsrd vec (reg_mem_to_gpr_mem val) idx (OperandSize.Size32)))
;; i64x2.replace_lane
(rule (vec_insert_lane $I64X2 vec val idx)
(pinsrd vec (gpr_mem_new val) idx (OperandSize.Size64)))
(pinsrd vec (reg_mem_to_gpr_mem val) idx (OperandSize.Size64)))
;; f32x4.replace_lane
(rule (vec_insert_lane $F32X4 vec val idx)
(insertps vec (xmm_mem_new val) (sse_insertps_lane_imm idx)))
(insertps vec (reg_mem_to_xmm_mem val) (sse_insertps_lane_imm idx)))
;; External rust code used to calculate the immediate value to `insertps`.
(decl sse_insertps_lane_imm (u8) u8)
@@ -1401,10 +1401,10 @@
;; internally as `xmm_rm_r` will merge the temp register into our `vec`
;; register.
(rule (vec_insert_lane $F64X2 vec (RegMem.Reg val) 0)
(movsd vec (xmm_mem_new (RegMem.Reg val))))
(movsd vec (reg_mem_to_xmm_mem (RegMem.Reg val))))
(rule (vec_insert_lane $F64X2 vec mem 0)
(movsd vec (xmm_to_xmm_mem (xmm_unary_rm_r (SseOpcode.Movsd)
(xmm_mem_new mem)))))
(reg_mem_to_xmm_mem mem)))))
;; f64x2.replace_lane 1
;;
@@ -1412,7 +1412,7 @@
;; into the second lane where unlike above cases we're not using the lane
;; immediate as an immediate to the instruction itself.
(rule (vec_insert_lane $F64X2 vec val 1)
(movlhps vec (xmm_mem_new val)))
(movlhps vec (reg_mem_to_xmm_mem val)))
;;;; Rules for `imax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;