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Intel encodings for floating point bitwise ops.

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band, bor, bxor, band_not are all available on XMM registers.
This commit is contained in:
Jakob Stoklund Olesen
2017-07-20 11:45:06 -07:00
parent 6ba604125d
commit 2b41f979cb
3 changed files with 111 additions and 5 deletions
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46
filetests/isa/intel/binary32-float.cton
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@@ -39,6 +39,29 @@ ebb0:
; asm: divss %xmm5, %xmm2
[-,%xmm2] v27 = fdiv v11, v10 ; bin: f3 0f 5e d5
; Bitwise ops.
; We use the *ps SSE instructions for everything because they are smaller.
; asm: andps %xmm2, %xmm5
[-,%xmm5] v30 = band v10, v11 ; bin: 0f 54 ea
; asm: andps %xmm5, %xmm2
[-,%xmm2] v31 = band v11, v10 ; bin: 0f 54 d5
; asm: andnps %xmm2, %xmm5
[-,%xmm5] v32 = band_not v10, v11 ; bin: 0f 55 ea
; asm: andnps %xmm5, %xmm2
[-,%xmm2] v33 = band_not v11, v10 ; bin: 0f 55 d5
; asm: orps %xmm2, %xmm5
[-,%xmm5] v34 = bor v10, v11 ; bin: 0f 56 ea
; asm: orps %xmm5, %xmm2
[-,%xmm2] v35 = bor v11, v10 ; bin: 0f 56 d5
; asm: xorps %xmm2, %xmm5
[-,%xmm5] v36 = bxor v10, v11 ; bin: 0f 57 ea
; asm: xorps %xmm5, %xmm2
[-,%xmm2] v37 = bxor v11, v10 ; bin: 0f 57 d5
return
}
@@ -74,5 +97,28 @@ ebb0:
; asm: divsd %xmm5, %xmm2
[-,%xmm2] v27 = fdiv v11, v10 ; bin: f2 0f 5e d5
; Bitwise ops.
; We use the *ps SSE instructions for everything because they are smaller.
; asm: andps %xmm2, %xmm5
[-,%xmm5] v30 = band v10, v11 ; bin: 0f 54 ea
; asm: andps %xmm5, %xmm2
[-,%xmm2] v31 = band v11, v10 ; bin: 0f 54 d5
; asm: andnps %xmm2, %xmm5
[-,%xmm5] v32 = band_not v10, v11 ; bin: 0f 55 ea
; asm: andnps %xmm5, %xmm2
[-,%xmm2] v33 = band_not v11, v10 ; bin: 0f 55 d5
; asm: orps %xmm2, %xmm5
[-,%xmm5] v34 = bor v10, v11 ; bin: 0f 56 ea
; asm: orps %xmm5, %xmm2
[-,%xmm2] v35 = bor v11, v10 ; bin: 0f 56 d5
; asm: xorps %xmm2, %xmm5
[-,%xmm5] v36 = bxor v10, v11 ; bin: 0f 57 ea
; asm: xorps %xmm5, %xmm2
[-,%xmm2] v37 = bxor v11, v10 ; bin: 0f 57 d5
return
}