Add use declarations for std features.

Merge the `use` parts of the `no_std` branch. This reduces the diffs
between master and the `no_std` branch, making it easier to maintain.

Most of these changes are derived from patches by @lachlansneff in
https://github.com/Cretonne/cretonne/tree/no_std.

lib/cretonne/src/regalloc/allocatable_set.rs

@@ -221,6 +221,7 @@ impl fmt::Display for AllocatableSet {
 mod tests {
     use super::*;
     use isa::registers::{RegClass, RegClassData};
+    use std::vec::Vec;
 
     // Register classes for testing.
     const GPR: RegClass = &RegClassData {

lib/cretonne/src/regalloc/coalescing.rs

@@ -18,6 +18,7 @@ use std::cmp;
 use std::iter;
 use std::fmt;
 use std::slice;
+use std::vec::Vec;
 use isa::{TargetIsa, EncInfo};
 use timing;
 

lib/cretonne/src/regalloc/diversion.rs

@@ -11,6 +11,7 @@ use ir::{Value, ValueLoc, ValueLocations, StackSlot};
 use ir::{InstructionData, Opcode};
 use isa::{RegUnit, RegInfo};
 use std::fmt;
+use std::vec::Vec;
 
 /// A diversion of a value from its original location to a new register or stack location.
 ///

lib/cretonne/src/regalloc/live_value_tracker.rs

@@ -13,6 +13,7 @@ use regalloc::affinity::Affinity;
 use regalloc::liveness::Liveness;
 use regalloc::liverange::LiveRange;
 use std::collections::HashMap;
+use std::vec::Vec;
 
 type ValueList = EntityList<Value>;
 

lib/cretonne/src/regalloc/liveness.rs

@@ -184,6 +184,7 @@ use regalloc::affinity::Affinity;
 use regalloc::liverange::{LiveRange, LiveRangeForest, LiveRangeContext};
 use std::mem;
 use std::ops::Index;
+use std::vec::Vec;
 use timing;
 
 /// A set of live ranges, indexed by value number.

lib/cretonne/src/regalloc/liverange.rs

@@ -463,6 +463,7 @@ mod tests {
     use entity::EntityRef;
     use ir::{ProgramOrder, ExpandedProgramPoint};
     use std::cmp::Ordering;
+    use std::vec::Vec;
 
     // Dummy program order which simply compares indexes.
     // It is assumed that EBBs have indexes that are multiples of 10, and instructions have indexes

lib/cretonne/src/regalloc/pressure.rs

@@ -273,6 +273,7 @@ mod tests {
     use regalloc::AllocatableSet;
     use std::borrow::Borrow;
     use super::Pressure;
+    use std::boxed::Box;
 
     // Make an arm32 `TargetIsa`, if possible.
     fn arm32() -> Option<Box<TargetIsa>> {

lib/cretonne/src/regalloc/reload.rs

@@ -21,6 +21,7 @@ use regalloc::live_value_tracker::{LiveValue, LiveValueTracker};
 use regalloc::liveness::Liveness;
 use timing;
 use topo_order::TopoOrder;
+use std::vec::Vec;
 
 /// Reusable data structures for the reload pass.
 pub struct Reload {

lib/cretonne/src/regalloc/solver.rs

@@ -108,6 +108,7 @@ use std::fmt;
 use std::mem;
 use super::AllocatableSet;
 use std::u16;
+use std::vec::Vec;
 
 /// A variable in the constraint problem.
 ///
@@ -1162,6 +1163,7 @@ mod tests {
     use isa::{TargetIsa, RegClass, RegUnit, RegInfo};
     use regalloc::AllocatableSet;
     use super::{Solver, Move};
+    use std::boxed::Box;
 
     // Make an arm32 `TargetIsa`, if possible.
     fn arm32() -> Option<Box<TargetIsa>> {

lib/cretonne/src/regalloc/spilling.rs

@@ -26,6 +26,7 @@ use regalloc::liveness::Liveness;
 use regalloc::pressure::Pressure;
 use regalloc::virtregs::VirtRegs;
 use std::fmt;
+use std::vec::Vec;
 use timing;
 use topo_order::TopoOrder;
 

lib/cretonne/src/regalloc/virtregs.rs

@@ -21,6 +21,7 @@ use packed_option::PackedOption;
 use ref_slice::ref_slice;
 use std::cmp::Ordering;
 use std::fmt;
+use std::vec::Vec;
 
 /// A virtual register reference.
 #[derive(Copy, Clone, PartialEq, Eq, Hash, PartialOrd, Ord)]