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Return a function pointer from TargetIsa::encode().

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Replace the isa::Legalize enumeration with a function pointer. This
allows an ISA to define its own specific legalization actions instead of
relying on the default two.

Generate a LEGALIZE_ACTIONS table for each ISA which contains
legalization function pointers indexed by the legalization codes that
are already in the encoding tables. Include this table in
isa/*/enc_tables.rs.

Give the `Encodings` iterator a reference to the action table and change
its `legalize()` method to return a function pointer instead of an
ISA-specific code.

The Result<> returned from TargetIsa::encode() no longer implements
Debug, so eliminate uses of unwrap and expect on that type.
This commit is contained in:
Jakob Stoklund Olesen
2017-07-27 14:46:56 -07:00
parent d1353bba05
commit 2aca35a9aa
19 changed files with 140 additions and 102 deletions
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3
lib/cretonne/src/isa/arm32/enc_tables.rs
View File

@@ -1,9 +1,10 @@
//! Encoding tables for ARM32 ISA.
use ir::types;
use isa::EncInfo;
use isa;
use isa::constraints::*;
use isa::enc_tables::*;
use isa::encoding::RecipeSizing;
include!(concat!(env!("OUT_DIR"), "/encoding-arm32.rs"));
include!(concat!(env!("OUT_DIR"), "/legalize-arm32.rs"));

1
lib/cretonne/src/isa/arm32/mod.rs
View File

@@ -72,6 +72,7 @@ impl TargetIsa for Isa {
self.cpumode,
&enc_tables::LEVEL2[..],
&enc_tables::ENCLISTS[..],
&enc_tables::LEGALIZE_ACTIONS[..],
&enc_tables::RECIPE_PREDICATES[..],
&enc_tables::INST_PREDICATES[..],
self.isa_flags.predicate_view())

3
lib/cretonne/src/isa/arm64/enc_tables.rs
View File

@@ -1,9 +1,10 @@
//! Encoding tables for ARM64 ISA.
use ir::types;
use isa::EncInfo;
use isa;
use isa::constraints::*;
use isa::enc_tables::*;
use isa::encoding::RecipeSizing;
include!(concat!(env!("OUT_DIR"), "/encoding-arm64.rs"));
include!(concat!(env!("OUT_DIR"), "/legalize-arm64.rs"));

1
lib/cretonne/src/isa/arm64/mod.rs
View File

@@ -65,6 +65,7 @@ impl TargetIsa for Isa {
&enc_tables::LEVEL1_A64[..],
&enc_tables::LEVEL2[..],
&enc_tables::ENCLISTS[..],
&enc_tables::LEGALIZE_ACTIONS[..],
&enc_tables::RECIPE_PREDICATES[..],
&enc_tables::INST_PREDICATES[..],
self.isa_flags.predicate_view())

11
lib/cretonne/src/isa/enc_tables.rs
View File

@@ -5,7 +5,7 @@
use constant_hash::{Table, probe};
use ir::{Type, Opcode, DataFlowGraph, InstructionData};
use isa::Encoding;
use isa::{Encoding, Legalize};
use settings::PredicateView;
use std::ops::Range;
@@ -109,6 +109,7 @@ pub fn lookup_enclist<'a, OffT1, OffT2>(ctrl_typevar: Type,
level1_table: &'static [Level1Entry<OffT1>],
level2_table: &'static [Level2Entry<OffT2>],
enclist: &'static [EncListEntry],
legalize_actions: &'static [Legalize],
recipe_preds: &'static [RecipePredicate],
inst_preds: &'static [InstPredicate],
isa_preds: PredicateView<'a>)
@@ -148,6 +149,7 @@ pub fn lookup_enclist<'a, OffT1, OffT2>(ctrl_typevar: Type,
inst,
dfg,
enclist,
legalize_actions,
recipe_preds,
inst_preds,
isa_preds)
@@ -173,6 +175,7 @@ pub struct Encodings<'a> {
inst: &'a InstructionData,
dfg: &'a DataFlowGraph,
enclist: &'static [EncListEntry],
legalize_actions: &'static [Legalize],
recipe_preds: &'static [RecipePredicate],
inst_preds: &'static [InstPredicate],
isa_preds: PredicateView<'a>,
@@ -189,6 +192,7 @@ impl<'a> Encodings<'a> {
inst: &'a InstructionData,
dfg: &'a DataFlowGraph,
enclist: &'static [EncListEntry],
legalize_actions: &'static [Legalize],
recipe_preds: &'static [RecipePredicate],
inst_preds: &'static [InstPredicate],
isa_preds: PredicateView<'a>)
@@ -202,6 +206,7 @@ impl<'a> Encodings<'a> {
recipe_preds,
inst_preds,
enclist,
legalize_actions,
}
}
@@ -210,9 +215,9 @@ impl<'a> Encodings<'a> {
/// instruction.
///
/// This method must only be called after the iterator returns `None`.
pub fn legalize(&self) -> LegalizeCode {
pub fn legalize(&self) -> Legalize {
debug_assert_eq!(self.offset, !0, "Premature Encodings::legalize()");
self.legalize
self.legalize_actions[self.legalize as usize]
}
/// Check if the `rpred` recipe predicate s satisfied.

3
lib/cretonne/src/isa/intel/enc_tables.rs
View File

@@ -1,7 +1,7 @@
//! Encoding tables for Intel ISAs.
use ir::{self, types, Opcode};
use isa::EncInfo;
use isa;
use isa::constraints::*;
use isa::enc_tables::*;
use isa::encoding::RecipeSizing;
@@ -9,3 +9,4 @@ use predicates;
use super::registers::*;
include!(concat!(env!("OUT_DIR"), "/encoding-intel.rs"));
include!(concat!(env!("OUT_DIR"), "/legalize-intel.rs"));

1
lib/cretonne/src/isa/intel/mod.rs
View File

@@ -72,6 +72,7 @@ impl TargetIsa for Isa {
self.cpumode,
&enc_tables::LEVEL2[..],
&enc_tables::ENCLISTS[..],
&enc_tables::LEGALIZE_ACTIONS[..],
&enc_tables::RECIPE_PREDICATES[..],
&enc_tables::INST_PREDICATES[..],
self.isa_flags.predicate_view())

29
lib/cretonne/src/isa/mod.rs
View File

@@ -45,6 +45,7 @@ pub use isa::encoding::{Encoding, EncInfo};
pub use isa::registers::{RegInfo, RegUnit, RegClass, RegClassIndex, regs_overlap};
use binemit;
use flowgraph;
use settings;
use ir;
use regalloc;
@@ -116,29 +117,11 @@ impl settings::Configurable for Builder {
/// After determining that an instruction doesn't have an encoding, how should we proceed to
/// legalize it?
///
/// These actions correspond to the transformation groups defined in `meta/cretonne/legalize.py`.
#[derive(Clone, Copy, PartialEq, Eq, Debug)]
pub enum Legalize {
/// Legalize in terms of narrower types.
Narrow,
/// Expanding in terms of other instructions using the same types.
Expand,
}
/// Translate a legalization code into a `Legalize` enum.
///
/// This mapping is going away soon. It depends on matching the `TargetISA.legalize_code()`
/// mapping.
impl From<u8> for Legalize {
fn from(x: u8) -> Legalize {
match x {
0 => Legalize::Narrow,
1 => Legalize::Expand,
_ => panic!("Unknown legalization code {}"),
}
}
}
/// The `Encodings` iterator returns a legalization function to call.
pub type Legalize = fn(&mut ir::DataFlowGraph,
&mut flowgraph::ControlFlowGraph,
&mut ir::Cursor)
-> bool;
/// Methods that are specialized to a target ISA.
pub trait TargetIsa {

3
lib/cretonne/src/isa/riscv/enc_tables.rs
View File

@@ -2,7 +2,7 @@
use ir::condcodes::IntCC;
use ir::{self, types, Opcode};
use isa::EncInfo;
use isa;
use isa::constraints::*;
use isa::enc_tables::*;
use isa::encoding::RecipeSizing;
@@ -16,3 +16,4 @@ use super::registers::*;
// - `ENCLIST`
// - `INFO`
include!(concat!(env!("OUT_DIR"), "/encoding-riscv.rs"));
include!(concat!(env!("OUT_DIR"), "/legalize-riscv.rs"));

32
lib/cretonne/src/isa/riscv/mod.rs
View File

@@ -72,6 +72,7 @@ impl TargetIsa for Isa {
self.cpumode,
&enc_tables::LEVEL2[..],
&enc_tables::ENCLISTS[..],
&enc_tables::LEGALIZE_ACTIONS[..],
&enc_tables::RECIPE_PREDICATES[..],
&enc_tables::INST_PREDICATES[..],
self.isa_flags.predicate_view())
@@ -113,8 +114,11 @@ mod tests {
use ir::{DataFlowGraph, InstructionData, Opcode};
use ir::{types, immediates};
fn encstr(isa: &isa::TargetIsa, enc: isa::Encoding) -> String {
isa.encoding_info().display(enc).to_string()
fn encstr(isa: &isa::TargetIsa, enc: Result<isa::Encoding, isa::Legalize>) -> String {
match enc {
Ok(e) => isa.encoding_info().display(e).to_string(),
Err(_) => "no encoding".to_string(),
}
}
#[test]
@@ -137,8 +141,7 @@ mod tests {
};
// ADDI is I/0b00100
assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst64, types::I64).unwrap()),
"I#04");
assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst64, types::I64)), "I#04");
// Try to encode iadd_imm.i64 v1, -10000.
let inst64_large = InstructionData::BinaryImm {
@@ -148,8 +151,7 @@ mod tests {
};
// Immediate is out of range for ADDI.
assert_eq!(isa.encode(&dfg, &inst64_large, types::I64),
Err(isa::Legalize::Expand));
assert!(isa.encode(&dfg, &inst64_large, types::I64).is_err());
// Create an iadd_imm.i32 which is encodable in RV64.
let inst32 = InstructionData::BinaryImm {
@@ -159,8 +161,7 @@ mod tests {
};
// ADDIW is I/0b00110
assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst32, types::I32).unwrap()),
"I#06");
assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst32, types::I32)), "I#06");
}
// Same as above, but for RV32.
@@ -184,8 +185,7 @@ mod tests {
};
// In 32-bit mode, an i64 bit add should be narrowed.
assert_eq!(isa.encode(&dfg, &inst64, types::I64),
Err(isa::Legalize::Narrow));
assert!(isa.encode(&dfg, &inst64, types::I64).is_err());
// Try to encode iadd_imm.i64 v1, -10000.
let inst64_large = InstructionData::BinaryImm {
@@ -195,8 +195,7 @@ mod tests {
};
// In 32-bit mode, an i64 bit add should be narrowed.
assert_eq!(isa.encode(&dfg, &inst64_large, types::I64),
Err(isa::Legalize::Narrow));
assert!(isa.encode(&dfg, &inst64_large, types::I64).is_err());
// Create an iadd_imm.i32 which is encodable in RV32.
let inst32 = InstructionData::BinaryImm {
@@ -206,8 +205,7 @@ mod tests {
};
// ADDI is I/0b00100
assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst32, types::I32).unwrap()),
"I#04");
assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst32, types::I32)), "I#04");
// Create an imul.i32 which is encodable in RV32, but only when use_m is true.
let mul32 = InstructionData::Binary {
@@ -215,8 +213,7 @@ mod tests {
args: [arg32, arg32],
};
assert_eq!(isa.encode(&dfg, &mul32, types::I32),
Err(isa::Legalize::Expand));
assert!(isa.encode(&dfg, &mul32, types::I32).is_err());
}
#[test]
@@ -241,7 +238,6 @@ mod tests {
opcode: Opcode::Imul,
args: [arg32, arg32],
};
assert_eq!(encstr(&*isa, isa.encode(&dfg, &mul32, types::I32).unwrap()),
"R#10c");
assert_eq!(encstr(&*isa, isa.encode(&dfg, &mul32, types::I32)), "R#10c");
}
}

21
lib/cretonne/src/legalizer/mod.rs
View File

@@ -15,9 +15,9 @@
use dominator_tree::DominatorTree;
use flowgraph::ControlFlowGraph;
use ir::{Function, Cursor, DataFlowGraph, InstructionData, Opcode, InstBuilder};
use ir::{self, Function, Cursor};
use ir::condcodes::IntCC;
use isa::{TargetIsa, Legalize};
use isa::TargetIsa;
use bitset::BitSet;
use ir::instructions::ValueTypeSet;
@@ -73,22 +73,7 @@ pub fn legalize_function(func: &mut Function,
Ok(encoding) => *func.encodings.ensure(inst) = encoding,
Err(action) => {
// We should transform the instruction into legal equivalents.
// Possible strategies are:
// 1. Legalize::Expand: Expand instruction into sequence of legal instructions.
// Possibly iteratively. ()
// 2. Legalize::Narrow: Split the controlling type variable into high and low
// parts. This applies both to SIMD vector types which can be halved and to
// integer types such as `i64` used on a 32-bit ISA. ().
// 3. TODO: Promote the controlling type variable to a larger type. This
// typically means expressing `i8` and `i16` arithmetic in terms if `i32`
// operations on RISC targets. (It may or may not be beneficial to promote
// small vector types versus splitting them.)
// 4. TODO: Convert to library calls. For example, floating point operations on
// an ISA with no IEEE 754 support.
let changed = match action {
Legalize::Expand => expand(&mut func.dfg, cfg, &mut pos),
Legalize::Narrow => narrow(&mut func.dfg, cfg, &mut pos),
};
let changed = action(&mut func.dfg, cfg, &mut pos);
// If the current instruction was replaced, we need to double back and revisit
// the expanded sequence. This is both to assign encodings and possible to
// expand further.

14
lib/cretonne/src/regalloc/coalescing.rs
View File

@@ -479,9 +479,10 @@ impl<'a> Context<'a> {
self.func.dfg.display_inst(pred_inst, self.isa));
// Give it an encoding.
let encoding = self.isa
.encode(&self.func.dfg, &self.func.dfg[inst], ty)
.expect("Can't encode copy");
let encoding = match self.isa.encode(&self.func.dfg, &self.func.dfg[inst], ty) {
Ok(e) => e,
Err(_) => panic!("Can't encode copy.{}", ty),
};
*self.func.encodings.ensure(inst) = encoding;
// Create a live range for the new value.
@@ -525,9 +526,10 @@ impl<'a> Context<'a> {
ty);
// Give it an encoding.
let encoding = self.isa
.encode(&self.func.dfg, &self.func.dfg[inst], ty)
.expect("Can't encode copy");
let encoding = match self.isa.encode(&self.func.dfg, &self.func.dfg[inst], ty) {
Ok(e) => e,
Err(_) => panic!("Can't encode copy.{}", ty),
};
*self.func.encodings.ensure(inst) = encoding;
// Create a live range for the new value.

14
lib/cretonne/src/regalloc/reload.rs
View File

@@ -220,9 +220,10 @@ impl<'a> Context<'a> {
let reg = dfg.ins(pos).fill(cand.value);
let fill = dfg.value_def(reg).unwrap_inst();
*encodings.ensure(fill) = self.isa
.encode(dfg, &dfg[fill], dfg.value_type(reg))
.expect("Can't encode fill");
match self.isa.encode(dfg, &dfg[fill], dfg.value_type(reg)) {
Ok(e) => *encodings.ensure(fill) = e,
Err(_) => panic!("Can't encode fill {}", cand.value),
}
self.reloads
.insert(ReloadedValue {
@@ -351,9 +352,10 @@ impl<'a> Context<'a> {
.Unary(Opcode::Spill, ty, reg);
// Give it an encoding.
*encodings.ensure(inst) = self.isa
.encode(dfg, &dfg[inst], ty)
.expect("Can't encode spill");
match self.isa.encode(dfg, &dfg[inst], ty) {
Ok(e) => *encodings.ensure(inst) = e,
Err(_) => panic!("Can't encode spill.{}", ty),
}
// Update live ranges.
self.liveness.move_def_locally(stack, inst);

8
lib/cretonne/src/regalloc/spilling.rs
View File

@@ -533,10 +533,10 @@ impl<'a> Context<'a> {
let ty = dfg.value_type(copy);
// Give it an encoding.
let encoding = self.isa
.encode(dfg, &dfg[inst], ty)
.expect("Can't encode copy");
*self.encodings.ensure(inst) = encoding;
match self.isa.encode(dfg, &dfg[inst], ty) {
Ok(e) => *self.encodings.ensure(inst) = e,
Err(_) => panic!("Can't encode {}", dfg.display_inst(inst, self.isa)),
}
// Update live ranges.
self.liveness.create_dead(copy, inst, Affinity::Reg(rci));

7
lib/cretonne/src/verifier/mod.rs
View File

@@ -697,11 +697,10 @@ impl<'a> Verifier<'a> {
isa.encoding_info().display(encoding));
}
}
Err(e) => {
Err(_) => {
return err!(inst,
"Instruction failed to re-encode {}: {:?}",
isa.encoding_info().display(encoding),
e)
"Instruction failed to re-encode {}",
isa.encoding_info().display(encoding))
}
}
return Ok(());