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Add spill/fill encodings for Intel ISAs.

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To begin with, these are catch-all encodings with a SIB byte and a
32-bit displacement, so they can access any stack slot via both the
stack pointer and the frame pointer.

In the future, we will add encodings for 8-bit displacements as well as
EBP-relative references without a SIB byte.
This commit is contained in:
Jakob Stoklund Olesen
2017-09-22 15:35:11 -07:00
parent 76eb7df9f0
commit 29dfcf5dfb
8 changed files with 217 additions and 6 deletions
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42
lib/cretonne/meta/isa/intel/recipes.py
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@@ -8,7 +8,7 @@ from base.formats import Unary, UnaryImm, Binary, BinaryImm, MultiAry
from base.formats import Trap, Call, IndirectCall, Store, Load
from base.formats import IntCompare
from base.formats import RegMove, Ternary, Jump, Branch, FuncAddr
from .registers import GPR, ABCD, FPR, GPR8, FPR8
from .registers import GPR, ABCD, FPR, GPR8, FPR8, StackGPR32, StackFPR32
try:
from typing import Tuple, Dict, Sequence # noqa
@@ -474,6 +474,26 @@ fstDisp32 = TailRecipe(
sink.put4(offset as u32);
''')
# Unary spill with SIB and 32-bit displacement.
spSib32 = TailRecipe(
'spSib32', Unary, size=6, ins=GPR, outs=StackGPR32,
emit='''
let base = stk_base(out_stk0.base);
PUT_OP(bits, rex2(base, in_reg0), sink);
modrm_sib_disp32(in_reg0, sink);
sib_noindex(base, sink);
sink.put4(out_stk0.offset as u32);
''')
fspSib32 = TailRecipe(
'fspSib32', Unary, size=6, ins=FPR, outs=StackFPR32,
emit='''
let base = stk_base(out_stk0.base);
PUT_OP(bits, rex2(base, in_reg0), sink);
modrm_sib_disp32(in_reg0, sink);
sib_noindex(base, sink);
sink.put4(out_stk0.offset as u32);
''')
#
# Load recipes
#
@@ -540,6 +560,26 @@ fldDisp32 = TailRecipe(
sink.put4(offset as u32);
''')
# Unary fill with SIB and 32-bit displacement.
fiSib32 = TailRecipe(
'fiSib32', Unary, size=6, ins=StackGPR32, outs=GPR,
emit='''
let base = stk_base(in_stk0.base);
PUT_OP(bits, rex2(base, out_reg0), sink);
modrm_sib_disp32(out_reg0, sink);
sib_noindex(base, sink);
sink.put4(in_stk0.offset as u32);
''')
ffiSib32 = TailRecipe(
'ffiSib32', Unary, size=6, ins=StackFPR32, outs=FPR,
emit='''
let base = stk_base(in_stk0.base);
PUT_OP(bits, rex2(base, out_reg0), sink);
modrm_sib_disp32(out_reg0, sink);
sib_noindex(base, sink);
sink.put4(in_stk0.offset as u32);
''')
#
# Call/return
#