Simplify "unimplemented" operation error message (#5429)
Now that all operations are implemented in ISLE, simplify Rust code by providing a generic error message if any operation is not implemented in ISLE. Done across all targets.
This commit is contained in:
Ulrich Weigand
@@ -15,7 +15,6 @@ use crate::isa::aarch64::inst::*;
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use crate::isa::aarch64::AArch64Backend;
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use crate::isa::aarch64::AArch64Backend;
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use crate::machinst::lower::*;
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use crate::machinst::lower::*;
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use crate::machinst::{Reg, Writable};
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use crate::machinst::{Reg, Writable};
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use crate::CodegenError;
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use crate::CodegenResult;
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use crate::CodegenResult;
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use crate::{machinst::*, trace};
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use crate::{machinst::*, trace};
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use smallvec::{smallvec, SmallVec};
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use smallvec::{smallvec, SmallVec};
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@@ -751,224 +750,19 @@ impl LowerBackend for AArch64Backend {
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return Ok(temp_regs);
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return Ok(temp_regs);
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}
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}
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let op = ctx.data(ir_inst).opcode();
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let ty = if ctx.num_outputs(ir_inst) > 0 {
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let ty = if ctx.num_outputs(ir_inst) > 0 {
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Some(ctx.output_ty(ir_inst, 0))
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Some(ctx.output_ty(ir_inst, 0))
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} else {
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} else {
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None
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None
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};
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};
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match op {
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Opcode::Iconst
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| Opcode::Null
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| Opcode::F32const
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| Opcode::F64const
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| Opcode::GetFramePointer
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| Opcode::GetStackPointer
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| Opcode::GetReturnAddress
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| Opcode::Iadd
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| Opcode::Isub
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| Opcode::UaddSat
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| Opcode::SaddSat
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| Opcode::UsubSat
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| Opcode::SsubSat
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| Opcode::Ineg
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| Opcode::Imul
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| Opcode::Umulhi
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| Opcode::Smulhi
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| Opcode::Udiv
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| Opcode::Sdiv
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| Opcode::Urem
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| Opcode::Srem
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| Opcode::Uextend
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| Opcode::Sextend
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| Opcode::Bnot
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| Opcode::Band
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| Opcode::Bor
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| Opcode::Bxor
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| Opcode::BandNot
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| Opcode::BorNot
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| Opcode::BxorNot
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| Opcode::Ishl
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| Opcode::Ushr
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| Opcode::Sshr
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| Opcode::Rotr
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| Opcode::Rotl
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| Opcode::Bitrev
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| Opcode::Clz
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| Opcode::Cls
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| Opcode::Ctz
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| Opcode::Bswap
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| Opcode::Popcnt
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| Opcode::Load
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| Opcode::Uload8
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| Opcode::Sload8
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| Opcode::Uload16
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| Opcode::Sload16
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| Opcode::Uload32
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| Opcode::Sload32
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| Opcode::Sload8x8
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| Opcode::Uload8x8
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| Opcode::Sload16x4
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| Opcode::Uload16x4
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| Opcode::Sload32x2
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| Opcode::Uload32x2
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| Opcode::Store
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| Opcode::Istore8
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| Opcode::Istore16
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| Opcode::Istore32
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| Opcode::StackAddr
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| Opcode::DynamicStackAddr
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| Opcode::AtomicRmw
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| Opcode::AtomicCas
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| Opcode::AtomicLoad
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| Opcode::AtomicStore
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| Opcode::Fence
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| Opcode::Nop
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| Opcode::Select
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| Opcode::SelectSpectreGuard
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| Opcode::Bitselect
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| Opcode::Vselect
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| Opcode::IsNull
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| Opcode::IsInvalid
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| Opcode::Ireduce
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| Opcode::Bmask
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| Opcode::Bitcast
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| Opcode::Return
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| Opcode::Icmp
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| Opcode::Fcmp
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| Opcode::Debugtrap
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| Opcode::Trap
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| Opcode::ResumableTrap
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| Opcode::FuncAddr
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| Opcode::SymbolValue
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| Opcode::Call
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| Opcode::CallIndirect
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| Opcode::GetPinnedReg
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| Opcode::SetPinnedReg
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| Opcode::Vconst
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| Opcode::Extractlane
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| Opcode::Insertlane
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| Opcode::Splat
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| Opcode::ScalarToVector
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| Opcode::VallTrue
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| Opcode::VanyTrue
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| Opcode::VhighBits
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| Opcode::Shuffle
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| Opcode::Swizzle
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| Opcode::Isplit
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| Opcode::Iconcat
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| Opcode::Smax
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| Opcode::Umax
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| Opcode::Umin
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| Opcode::Smin
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| Opcode::IaddPairwise
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| Opcode::WideningPairwiseDotProductS
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| Opcode::Fadd
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| Opcode::Fsub
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| Opcode::Fmul
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| Opcode::Fdiv
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| Opcode::Fmin
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| Opcode::Fmax
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| Opcode::FminPseudo
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| Opcode::FmaxPseudo
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| Opcode::Sqrt
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| Opcode::Fneg
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| Opcode::Fabs
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| Opcode::Fpromote
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| Opcode::Fdemote
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| Opcode::Ceil
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| Opcode::Floor
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| Opcode::Trunc
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| Opcode::Nearest
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| Opcode::Fma
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| Opcode::Fcopysign
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| Opcode::FcvtToUint
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| Opcode::FcvtToSint
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| Opcode::FcvtFromUint
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| Opcode::FcvtFromSint
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| Opcode::FcvtToUintSat
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| Opcode::FcvtToSintSat
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| Opcode::UaddOverflowTrap
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| Opcode::IaddCout
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| Opcode::Iabs
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| Opcode::AvgRound
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| Opcode::Snarrow
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| Opcode::Unarrow
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| Opcode::Uunarrow
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| Opcode::SwidenLow
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| Opcode::SwidenHigh
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| Opcode::UwidenLow
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| Opcode::UwidenHigh
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| Opcode::TlsValue
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| Opcode::SqmulRoundSat
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| Opcode::FcvtLowFromSint
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| Opcode::FvpromoteLow
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| Opcode::Fvdemote
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| Opcode::ExtractVector => {
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unreachable!(
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unreachable!(
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"implemented in ISLE: inst = `{}`, type = `{:?}`",
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"not implemented in ISLE: inst = `{}`, type = `{:?}`",
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ctx.dfg().display_inst(ir_inst),
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ctx.dfg().display_inst(ir_inst),
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ty
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ty
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);
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);
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}
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}
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Opcode::StackLoad
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| Opcode::StackStore
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| Opcode::DynamicStackStore
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| Opcode::DynamicStackLoad => {
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panic!("Direct stack memory access not supported; should not be used by Wasm");
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}
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Opcode::HeapLoad | Opcode::HeapStore | Opcode::HeapAddr => {
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panic!("heap access instructions should have been removed by legalization!");
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}
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Opcode::TableAddr => {
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panic!("table_addr should have been removed by legalization!");
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}
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Opcode::Trapz | Opcode::Trapnz | Opcode::ResumableTrapnz => {
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panic!(
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"trapz / trapnz / resumable_trapnz should have been removed by legalization!"
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);
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}
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Opcode::GlobalValue => {
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panic!("global_value should have been removed by legalization!");
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}
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Opcode::Jump | Opcode::Brz | Opcode::Brnz | Opcode::BrTable => {
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panic!("Branch opcode reached non-branch lowering logic!");
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}
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Opcode::IaddImm
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| Opcode::ImulImm
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| Opcode::UdivImm
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| Opcode::SdivImm
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| Opcode::UremImm
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| Opcode::SremImm
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| Opcode::IrsubImm
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| Opcode::IaddCin
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| Opcode::IaddCarry
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| Opcode::IsubBin
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| Opcode::IsubBout
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| Opcode::IsubBorrow
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| Opcode::BandImm
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| Opcode::BorImm
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| Opcode::BxorImm
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| Opcode::RotlImm
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| Opcode::RotrImm
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| Opcode::IshlImm
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| Opcode::UshrImm
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| Opcode::SshrImm
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| Opcode::IcmpImm => {
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panic!("ALU+imm and ALU+carry ops should not appear here!");
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}
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Opcode::Vconcat | Opcode::Vsplit => {
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return Err(CodegenError::Unsupported(format!(
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"Unimplemented lowering: {}",
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op
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)));
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}
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}
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}
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fn lower_branch_group(
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fn lower_branch_group(
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&self,
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&self,
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ctx: &mut Lower<Inst>,
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ctx: &mut Lower<Inst>,
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@@ -993,7 +787,7 @@ impl LowerBackend for AArch64Backend {
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}
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}
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unreachable!(
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unreachable!(
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"implemented in ISLE: branch = `{}`",
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"not implemented in ISLE: branch = `{}`",
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ctx.dfg().display_inst(branches[0]),
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ctx.dfg().display_inst(branches[0]),
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);
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);
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}
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}
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@@ -55,8 +55,9 @@ impl LowerBackend for Riscv64Backend {
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assert!(temp_regs.len() == 0);
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assert!(temp_regs.len() == 0);
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return Ok(());
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return Ok(());
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}
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}
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unreachable!(
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unreachable!(
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"implemented in ISLE: branch = `{}`",
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"not implemented in ISLE: branch = `{}`",
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ctx.dfg().display_inst(branches[0]),
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ctx.dfg().display_inst(branches[0]),
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);
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);
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}
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}
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@@ -20,221 +20,17 @@ impl LowerBackend for S390xBackend {
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return Ok(temp_regs);
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return Ok(temp_regs);
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}
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}
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let op = ctx.data(ir_inst).opcode();
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let ty = if ctx.num_outputs(ir_inst) > 0 {
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let ty = if ctx.num_outputs(ir_inst) > 0 {
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Some(ctx.output_ty(ir_inst, 0))
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Some(ctx.output_ty(ir_inst, 0))
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} else {
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} else {
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None
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None
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};
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};
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match op {
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Opcode::Nop
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| Opcode::Iconst
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| Opcode::F32const
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| Opcode::F64const
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| Opcode::Vconst
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| Opcode::Null
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| Opcode::Isplit
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| Opcode::Iconcat
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| Opcode::Iadd
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| Opcode::Isub
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| Opcode::UaddSat
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| Opcode::SaddSat
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| Opcode::UsubSat
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| Opcode::SsubSat
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| Opcode::IaddPairwise
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| Opcode::Smin
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| Opcode::Umin
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| Opcode::Smax
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| Opcode::Umax
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| Opcode::AvgRound
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| Opcode::Iabs
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| Opcode::Ineg
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| Opcode::Imul
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| Opcode::Umulhi
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| Opcode::Smulhi
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| Opcode::WideningPairwiseDotProductS
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| Opcode::SqmulRoundSat
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| Opcode::Udiv
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| Opcode::Urem
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| Opcode::Sdiv
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| Opcode::Srem
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| Opcode::Ishl
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| Opcode::Ushr
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| Opcode::Sshr
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| Opcode::Rotr
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| Opcode::Rotl
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| Opcode::Ireduce
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| Opcode::Uextend
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| Opcode::Sextend
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| Opcode::Snarrow
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| Opcode::Unarrow
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| Opcode::Uunarrow
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| Opcode::SwidenLow
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| Opcode::SwidenHigh
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| Opcode::UwidenLow
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| Opcode::UwidenHigh
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| Opcode::Bnot
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| Opcode::Band
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| Opcode::Bor
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| Opcode::Bxor
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| Opcode::BandNot
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| Opcode::BorNot
|
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| Opcode::BxorNot
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| Opcode::Bitselect
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| Opcode::Vselect
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| Opcode::Bmask
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| Opcode::Bitrev
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| Opcode::Bswap
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| Opcode::Clz
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| Opcode::Cls
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| Opcode::Ctz
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| Opcode::Popcnt
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| Opcode::Fadd
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| Opcode::Fsub
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| Opcode::Fmul
|
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| Opcode::Fdiv
|
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| Opcode::Fmin
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| Opcode::Fmax
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| Opcode::FminPseudo
|
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| Opcode::FmaxPseudo
|
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| Opcode::Sqrt
|
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| Opcode::Fneg
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| Opcode::Fabs
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| Opcode::Fpromote
|
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| Opcode::Fdemote
|
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| Opcode::FvpromoteLow
|
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| Opcode::Fvdemote
|
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| Opcode::Ceil
|
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| Opcode::Floor
|
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| Opcode::Trunc
|
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| Opcode::Nearest
|
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| Opcode::Fma
|
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| Opcode::Fcopysign
|
|
||||||
| Opcode::FcvtFromUint
|
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| Opcode::FcvtFromSint
|
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| Opcode::FcvtLowFromSint
|
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||||||
| Opcode::FcvtToUint
|
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| Opcode::FcvtToSint
|
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| Opcode::FcvtToUintSat
|
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| Opcode::FcvtToSintSat
|
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||||||
| Opcode::Splat
|
|
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| Opcode::Swizzle
|
|
||||||
| Opcode::Shuffle
|
|
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| Opcode::Insertlane
|
|
||||||
| Opcode::Extractlane
|
|
||||||
| Opcode::ScalarToVector
|
|
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| Opcode::VhighBits
|
|
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| Opcode::Bitcast
|
|
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| Opcode::Load
|
|
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| Opcode::Uload8
|
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| Opcode::Sload8
|
|
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| Opcode::Uload16
|
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| Opcode::Sload16
|
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||||||
| Opcode::Uload32
|
|
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| Opcode::Sload32
|
|
||||||
| Opcode::Uload8x8
|
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||||||
| Opcode::Sload8x8
|
|
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| Opcode::Uload16x4
|
|
||||||
| Opcode::Sload16x4
|
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||||||
| Opcode::Uload32x2
|
|
||||||
| Opcode::Sload32x2
|
|
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| Opcode::Store
|
|
||||||
| Opcode::Istore8
|
|
||||||
| Opcode::Istore16
|
|
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| Opcode::Istore32
|
|
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| Opcode::AtomicRmw
|
|
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| Opcode::AtomicCas
|
|
||||||
| Opcode::AtomicLoad
|
|
||||||
| Opcode::AtomicStore
|
|
||||||
| Opcode::Fence
|
|
||||||
| Opcode::Icmp
|
|
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| Opcode::Fcmp
|
|
||||||
| Opcode::VanyTrue
|
|
||||||
| Opcode::VallTrue
|
|
||||||
| Opcode::IsNull
|
|
||||||
| Opcode::IsInvalid
|
|
||||||
| Opcode::Select
|
|
||||||
| Opcode::SelectSpectreGuard
|
|
||||||
| Opcode::Trap
|
|
||||||
| Opcode::ResumableTrap
|
|
||||||
| Opcode::Trapz
|
|
||||||
| Opcode::Trapnz
|
|
||||||
| Opcode::ResumableTrapnz
|
|
||||||
| Opcode::Debugtrap
|
|
||||||
| Opcode::UaddOverflowTrap
|
|
||||||
| Opcode::Call
|
|
||||||
| Opcode::CallIndirect
|
|
||||||
| Opcode::Return
|
|
||||||
| Opcode::StackAddr
|
|
||||||
| Opcode::FuncAddr
|
|
||||||
| Opcode::SymbolValue
|
|
||||||
| Opcode::TlsValue
|
|
||||||
| Opcode::GetFramePointer
|
|
||||||
| Opcode::GetStackPointer
|
|
||||||
| Opcode::GetReturnAddress => {
|
|
||||||
unreachable!(
|
unreachable!(
|
||||||
"implemented in ISLE: inst = `{}`, type = `{:?}`",
|
"not implemented in ISLE: inst = `{}`, type = `{:?}`",
|
||||||
ctx.dfg().display_inst(ir_inst),
|
ctx.dfg().display_inst(ir_inst),
|
||||||
ty
|
ty
|
||||||
)
|
);
|
||||||
}
|
|
||||||
|
|
||||||
Opcode::GetPinnedReg
|
|
||||||
| Opcode::SetPinnedReg
|
|
||||||
| Opcode::Vsplit
|
|
||||||
| Opcode::Vconcat
|
|
||||||
| Opcode::DynamicStackLoad
|
|
||||||
| Opcode::DynamicStackStore
|
|
||||||
| Opcode::DynamicStackAddr
|
|
||||||
| Opcode::ExtractVector => {
|
|
||||||
unreachable!(
|
|
||||||
"TODO: not yet implemented in ISLE: inst = `{}`, type = `{:?}`",
|
|
||||||
ctx.dfg().display_inst(ir_inst),
|
|
||||||
ty
|
|
||||||
)
|
|
||||||
}
|
|
||||||
|
|
||||||
Opcode::StackLoad | Opcode::StackStore => {
|
|
||||||
panic!("Direct stack memory access not supported; should not be used by Wasm");
|
|
||||||
}
|
|
||||||
Opcode::HeapLoad | Opcode::HeapStore | Opcode::HeapAddr => {
|
|
||||||
panic!("heap access instructions should have been removed by legalization!");
|
|
||||||
}
|
|
||||||
Opcode::TableAddr => {
|
|
||||||
panic!("table_addr should have been removed by legalization!");
|
|
||||||
}
|
|
||||||
Opcode::GlobalValue => {
|
|
||||||
panic!("global_value should have been removed by legalization!");
|
|
||||||
}
|
|
||||||
Opcode::Jump | Opcode::Brz | Opcode::Brnz | Opcode::BrTable => {
|
|
||||||
panic!("Branch opcode reached non-branch lowering logic!");
|
|
||||||
}
|
|
||||||
Opcode::IaddImm
|
|
||||||
| Opcode::ImulImm
|
|
||||||
| Opcode::UdivImm
|
|
||||||
| Opcode::SdivImm
|
|
||||||
| Opcode::UremImm
|
|
||||||
| Opcode::SremImm
|
|
||||||
| Opcode::IrsubImm
|
|
||||||
| Opcode::IaddCin
|
|
||||||
| Opcode::IaddCout
|
|
||||||
| Opcode::IaddCarry
|
|
||||||
| Opcode::IsubBin
|
|
||||||
| Opcode::IsubBout
|
|
||||||
| Opcode::IsubBorrow
|
|
||||||
| Opcode::BandImm
|
|
||||||
| Opcode::BorImm
|
|
||||||
| Opcode::BxorImm
|
|
||||||
| Opcode::RotlImm
|
|
||||||
| Opcode::RotrImm
|
|
||||||
| Opcode::IshlImm
|
|
||||||
| Opcode::UshrImm
|
|
||||||
| Opcode::SshrImm
|
|
||||||
| Opcode::IcmpImm => {
|
|
||||||
panic!("ALU+imm and ALU+carry ops should not appear here!");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
fn lower_branch_group(
|
fn lower_branch_group(
|
||||||
@@ -261,8 +57,9 @@ impl LowerBackend for S390xBackend {
|
|||||||
assert!(temp_regs.len() == 0);
|
assert!(temp_regs.len() == 0);
|
||||||
return Ok(());
|
return Ok(());
|
||||||
}
|
}
|
||||||
|
|
||||||
unreachable!(
|
unreachable!(
|
||||||
"implemented in ISLE: branch = `{}`",
|
"not implemented in ISLE: branch = `{}`",
|
||||||
ctx.dfg().display_inst(branches[0]),
|
ctx.dfg().display_inst(branches[0]),
|
||||||
);
|
);
|
||||||
}
|
}
|
||||||
|
|||||||
@@ -304,237 +304,19 @@ impl LowerBackend for X64Backend {
|
|||||||
return Ok(temp_regs);
|
return Ok(temp_regs);
|
||||||
}
|
}
|
||||||
|
|
||||||
let op = ctx.data(ir_inst).opcode();
|
|
||||||
let ty = if ctx.num_outputs(ir_inst) > 0 {
|
let ty = if ctx.num_outputs(ir_inst) > 0 {
|
||||||
Some(ctx.output_ty(ir_inst, 0))
|
Some(ctx.output_ty(ir_inst, 0))
|
||||||
} else {
|
} else {
|
||||||
None
|
None
|
||||||
};
|
};
|
||||||
|
|
||||||
match op {
|
|
||||||
Opcode::Iconst
|
|
||||||
| Opcode::F32const
|
|
||||||
| Opcode::F64const
|
|
||||||
| Opcode::Null
|
|
||||||
| Opcode::Iadd
|
|
||||||
| Opcode::IaddCout
|
|
||||||
| Opcode::SaddSat
|
|
||||||
| Opcode::UaddSat
|
|
||||||
| Opcode::Isub
|
|
||||||
| Opcode::SsubSat
|
|
||||||
| Opcode::UsubSat
|
|
||||||
| Opcode::AvgRound
|
|
||||||
| Opcode::Band
|
|
||||||
| Opcode::Bor
|
|
||||||
| Opcode::Bxor
|
|
||||||
| Opcode::Imul
|
|
||||||
| Opcode::BandNot
|
|
||||||
| Opcode::Iabs
|
|
||||||
| Opcode::Smax
|
|
||||||
| Opcode::Umax
|
|
||||||
| Opcode::Smin
|
|
||||||
| Opcode::Umin
|
|
||||||
| Opcode::Bnot
|
|
||||||
| Opcode::Bitselect
|
|
||||||
| Opcode::Vselect
|
|
||||||
| Opcode::Ushr
|
|
||||||
| Opcode::Sshr
|
|
||||||
| Opcode::Ishl
|
|
||||||
| Opcode::Rotl
|
|
||||||
| Opcode::Rotr
|
|
||||||
| Opcode::Ineg
|
|
||||||
| Opcode::Trap
|
|
||||||
| Opcode::ResumableTrap
|
|
||||||
| Opcode::UaddOverflowTrap
|
|
||||||
| Opcode::Clz
|
|
||||||
| Opcode::Ctz
|
|
||||||
| Opcode::Popcnt
|
|
||||||
| Opcode::Bitrev
|
|
||||||
| Opcode::Bswap
|
|
||||||
| Opcode::IsNull
|
|
||||||
| Opcode::IsInvalid
|
|
||||||
| Opcode::Uextend
|
|
||||||
| Opcode::Sextend
|
|
||||||
| Opcode::Ireduce
|
|
||||||
| Opcode::Debugtrap
|
|
||||||
| Opcode::WideningPairwiseDotProductS
|
|
||||||
| Opcode::Fadd
|
|
||||||
| Opcode::Fsub
|
|
||||||
| Opcode::Fmul
|
|
||||||
| Opcode::Fdiv
|
|
||||||
| Opcode::Fmin
|
|
||||||
| Opcode::Fmax
|
|
||||||
| Opcode::FminPseudo
|
|
||||||
| Opcode::FmaxPseudo
|
|
||||||
| Opcode::Sqrt
|
|
||||||
| Opcode::Fpromote
|
|
||||||
| Opcode::FvpromoteLow
|
|
||||||
| Opcode::Fdemote
|
|
||||||
| Opcode::Fvdemote
|
|
||||||
| Opcode::Fma
|
|
||||||
| Opcode::Icmp
|
|
||||||
| Opcode::Fcmp
|
|
||||||
| Opcode::Load
|
|
||||||
| Opcode::Uload8
|
|
||||||
| Opcode::Sload8
|
|
||||||
| Opcode::Uload16
|
|
||||||
| Opcode::Sload16
|
|
||||||
| Opcode::Uload32
|
|
||||||
| Opcode::Sload32
|
|
||||||
| Opcode::Sload8x8
|
|
||||||
| Opcode::Uload8x8
|
|
||||||
| Opcode::Sload16x4
|
|
||||||
| Opcode::Uload16x4
|
|
||||||
| Opcode::Sload32x2
|
|
||||||
| Opcode::Uload32x2
|
|
||||||
| Opcode::Store
|
|
||||||
| Opcode::Istore8
|
|
||||||
| Opcode::Istore16
|
|
||||||
| Opcode::Istore32
|
|
||||||
| Opcode::AtomicRmw
|
|
||||||
| Opcode::AtomicCas
|
|
||||||
| Opcode::AtomicLoad
|
|
||||||
| Opcode::AtomicStore
|
|
||||||
| Opcode::Fence
|
|
||||||
| Opcode::FuncAddr
|
|
||||||
| Opcode::SymbolValue
|
|
||||||
| Opcode::Return
|
|
||||||
| Opcode::Call
|
|
||||||
| Opcode::CallIndirect
|
|
||||||
| Opcode::GetFramePointer
|
|
||||||
| Opcode::GetStackPointer
|
|
||||||
| Opcode::GetReturnAddress
|
|
||||||
| Opcode::Select
|
|
||||||
| Opcode::SelectSpectreGuard
|
|
||||||
| Opcode::FcvtFromSint
|
|
||||||
| Opcode::FcvtLowFromSint
|
|
||||||
| Opcode::FcvtFromUint
|
|
||||||
| Opcode::FcvtToUint
|
|
||||||
| Opcode::FcvtToSint
|
|
||||||
| Opcode::FcvtToUintSat
|
|
||||||
| Opcode::FcvtToSintSat
|
|
||||||
| Opcode::IaddPairwise
|
|
||||||
| Opcode::UwidenHigh
|
|
||||||
| Opcode::UwidenLow
|
|
||||||
| Opcode::SwidenHigh
|
|
||||||
| Opcode::SwidenLow
|
|
||||||
| Opcode::Snarrow
|
|
||||||
| Opcode::Unarrow
|
|
||||||
| Opcode::Bitcast
|
|
||||||
| Opcode::Fabs
|
|
||||||
| Opcode::Fneg
|
|
||||||
| Opcode::Fcopysign
|
|
||||||
| Opcode::Ceil
|
|
||||||
| Opcode::Floor
|
|
||||||
| Opcode::Nearest
|
|
||||||
| Opcode::Trunc
|
|
||||||
| Opcode::StackAddr
|
|
||||||
| Opcode::Udiv
|
|
||||||
| Opcode::Urem
|
|
||||||
| Opcode::Sdiv
|
|
||||||
| Opcode::Srem
|
|
||||||
| Opcode::Umulhi
|
|
||||||
| Opcode::Smulhi
|
|
||||||
| Opcode::GetPinnedReg
|
|
||||||
| Opcode::SetPinnedReg
|
|
||||||
| Opcode::Vconst
|
|
||||||
| Opcode::Insertlane
|
|
||||||
| Opcode::Shuffle
|
|
||||||
| Opcode::Swizzle
|
|
||||||
| Opcode::Extractlane
|
|
||||||
| Opcode::ScalarToVector
|
|
||||||
| Opcode::Splat
|
|
||||||
| Opcode::VanyTrue
|
|
||||||
| Opcode::VallTrue
|
|
||||||
| Opcode::VhighBits
|
|
||||||
| Opcode::Iconcat
|
|
||||||
| Opcode::Isplit
|
|
||||||
| Opcode::TlsValue
|
|
||||||
| Opcode::SqmulRoundSat
|
|
||||||
| Opcode::Uunarrow
|
|
||||||
| Opcode::Nop
|
|
||||||
| Opcode::Bmask => {
|
|
||||||
unreachable!(
|
unreachable!(
|
||||||
"implemented in ISLE: inst = `{}`, type = `{:?}`",
|
"not implemented in ISLE: inst = `{}`, type = `{:?}`",
|
||||||
ctx.dfg().display_inst(ir_inst),
|
ctx.dfg().display_inst(ir_inst),
|
||||||
ty
|
ty
|
||||||
)
|
|
||||||
}
|
|
||||||
|
|
||||||
Opcode::DynamicStackAddr => unimplemented!("DynamicStackAddr"),
|
|
||||||
|
|
||||||
// Unimplemented opcodes below. These are not currently used by Wasm
|
|
||||||
// lowering or other known embeddings, but should be either supported or
|
|
||||||
// removed eventually
|
|
||||||
Opcode::ExtractVector => {
|
|
||||||
unimplemented!("ExtractVector not supported");
|
|
||||||
}
|
|
||||||
|
|
||||||
Opcode::Cls => unimplemented!("Cls not supported"),
|
|
||||||
|
|
||||||
Opcode::BorNot | Opcode::BxorNot => {
|
|
||||||
unimplemented!("or-not / xor-not opcodes not implemented");
|
|
||||||
}
|
|
||||||
|
|
||||||
Opcode::Vsplit | Opcode::Vconcat => {
|
|
||||||
unimplemented!("Vector split/concat ops not implemented.");
|
|
||||||
}
|
|
||||||
|
|
||||||
Opcode::IaddImm
|
|
||||||
| Opcode::ImulImm
|
|
||||||
| Opcode::UdivImm
|
|
||||||
| Opcode::SdivImm
|
|
||||||
| Opcode::UremImm
|
|
||||||
| Opcode::SremImm
|
|
||||||
| Opcode::IrsubImm
|
|
||||||
| Opcode::IaddCin
|
|
||||||
| Opcode::IaddCarry
|
|
||||||
| Opcode::IsubBin
|
|
||||||
| Opcode::IsubBout
|
|
||||||
| Opcode::IsubBorrow
|
|
||||||
| Opcode::BandImm
|
|
||||||
| Opcode::BorImm
|
|
||||||
| Opcode::BxorImm
|
|
||||||
| Opcode::RotlImm
|
|
||||||
| Opcode::RotrImm
|
|
||||||
| Opcode::IshlImm
|
|
||||||
| Opcode::UshrImm
|
|
||||||
| Opcode::SshrImm
|
|
||||||
| Opcode::IcmpImm => {
|
|
||||||
panic!("ALU+imm and ALU+carry ops should not appear here!");
|
|
||||||
}
|
|
||||||
|
|
||||||
Opcode::StackLoad
|
|
||||||
| Opcode::StackStore
|
|
||||||
| Opcode::DynamicStackStore
|
|
||||||
| Opcode::DynamicStackLoad => {
|
|
||||||
panic!("Direct stack memory access not supported; should have been legalized");
|
|
||||||
}
|
|
||||||
|
|
||||||
Opcode::GlobalValue => {
|
|
||||||
panic!("global_value should have been removed by legalization!");
|
|
||||||
}
|
|
||||||
|
|
||||||
Opcode::HeapLoad | Opcode::HeapStore | Opcode::HeapAddr => {
|
|
||||||
panic!("heap access instructions should have been removed by legalization!");
|
|
||||||
}
|
|
||||||
|
|
||||||
Opcode::TableAddr => {
|
|
||||||
panic!("table_addr should have been removed by legalization!");
|
|
||||||
}
|
|
||||||
|
|
||||||
Opcode::Trapz | Opcode::Trapnz | Opcode::ResumableTrapnz => {
|
|
||||||
panic!(
|
|
||||||
"trapz / trapnz / resumable_trapnz should have been removed by legalization!"
|
|
||||||
);
|
);
|
||||||
}
|
}
|
||||||
|
|
||||||
Opcode::Jump | Opcode::Brz | Opcode::Brnz | Opcode::BrTable => {
|
|
||||||
panic!("Branch opcode reached non-branch lowering logic!");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
fn lower_branch_group(
|
fn lower_branch_group(
|
||||||
&self,
|
&self,
|
||||||
ctx: &mut Lower<Inst>,
|
ctx: &mut Lower<Inst>,
|
||||||
@@ -559,7 +341,7 @@ impl LowerBackend for X64Backend {
|
|||||||
}
|
}
|
||||||
|
|
||||||
unreachable!(
|
unreachable!(
|
||||||
"implemented in ISLE: branch = `{}`",
|
"not implemented in ISLE: branch = `{}`",
|
||||||
ctx.dfg().display_inst(branches[0]),
|
ctx.dfg().display_inst(branches[0]),
|
||||||
);
|
);
|
||||||
}
|
}
|
||||||
|
|||||||
Reference in New Issue
Block a user